From 8280e10521c7754b713137728e12e0ecbcac40b0 Mon Sep 17 00:00:00 2001 From: Nuno Brum Date: Thu, 10 Aug 2023 12:13:39 +0200 Subject: [PATCH] Aligning documentation to the new folder structure. Including the new AscEditor class on the description --- PyLTSpice/sim/tookit/__init__.py | 0 .../failure_modes.py} | 43 +++----------- PyLTSpice/sim/tookit/montecarlo.py | 19 +++++++ PyLTSpice/sim/tookit/sim_analysis.py | 56 +++++++++++++++++++ doc/classes/SpiceCircuit.rst | 7 --- doc/classes/SpiceEditor.rst | 7 --- doc/classes/asc_editor.rst | 9 +++ doc/classes/editor_classes.rst | 9 +++ doc/classes/raw_classes.rst | 13 +++++ doc/classes/sim_client.rst | 5 +- doc/classes/sim_server.rst | 5 +- .../{classes.rst => simulation_classes.rst} | 13 ++--- doc/classes/spice_circuit.rst | 2 +- doc/classes/spice_editor.rst | 2 +- doc/classes/trace.rst | 7 ++- doc/classes/write_trace.rst | 2 +- 16 files changed, 133 insertions(+), 66 deletions(-) create mode 100644 PyLTSpice/sim/tookit/__init__.py rename PyLTSpice/sim/{sim_analysis.py => tookit/failure_modes.py} (70%) create mode 100644 PyLTSpice/sim/tookit/montecarlo.py create mode 100644 PyLTSpice/sim/tookit/sim_analysis.py delete mode 100644 doc/classes/SpiceCircuit.rst delete mode 100644 doc/classes/SpiceEditor.rst create mode 100644 doc/classes/asc_editor.rst create mode 100644 doc/classes/editor_classes.rst create mode 100644 doc/classes/raw_classes.rst rename doc/classes/{classes.rst => simulation_classes.rst} (62%) diff --git a/PyLTSpice/sim/tookit/__init__.py b/PyLTSpice/sim/tookit/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/PyLTSpice/sim/sim_analysis.py b/PyLTSpice/sim/tookit/failure_modes.py similarity index 70% rename from PyLTSpice/sim/sim_analysis.py rename to PyLTSpice/sim/tookit/failure_modes.py index 5a4b3df..c043bf1 100644 --- a/PyLTSpice/sim/sim_analysis.py +++ b/PyLTSpice/sim/tookit/failure_modes.py @@ -9,49 +9,22 @@ # |_| \__, |_____|_| |____/| .__/|_|\___\___| # |___/ |_| # -# Name: sim_analysis.py -# Purpose: Classes to automate Monte-Carlo, FMEA or Worst Case Analysis -# be updated by user instructions +# Name: failure_modes.py +# Purpose: Class to automate FMEA # # Author: Nuno Brum (nuno.brum@gmail.com) # -# Created: 23-12-2016 +# Created: 10-08-2023 # Licence: refer to the LICENSE file # ------------------------------------------------------------------------------- from collections import OrderedDict -from typing import Iterable, Union, Optional +from typing import Union, Optional, Iterable -from .sim_runner import AnyRunner -from ..editor.base_editor import BaseEditor, ComponentNotFoundError -from ..sim.simulator import Simulator - - -class SimAnalysis(object): - """ - Base class for making Monte-Carlo, Extreme Value Analysis (EVA) or Failure Mode and Effects Analysis. - As a base class, a certain number of assertions must be made on the simulation results that will make the pass/fail. - - Note: For the time being only measurements done with .MEAS are possible. At a later stage the parsing of RAW files - will be possible, although, it seems that the later solution is less computing intense. - """ - - def __init__(self, circuit_file: Union[str, BaseEditor], simulator: Optional[Simulator] = None, - runner: Optional[AnyRunner] = None): - if isinstance(circuit_file, str): - from ..editor.spice_editor import SpiceEditor - self.editor = SpiceEditor(circuit_file) - else: - self.editor = circuit_file - if simulator is None: - from ..sim.ltspice_simulator import LTspice - self.simulator = LTspice() - else: - self.simulator = simulator - if runner is None: - from ..sim.sim_runner import SimRunner - self.runner = SimRunner(parallel_sims=1, timeout=None, verbose=False, output_folder=None) - self.simulations = OrderedDict() +from editor.base_editor import BaseEditor, ComponentNotFoundError +from .sim_analysis import SimAnalysis +from sim.sim_runner import AnyRunner +from sim.simulator import Simulator class FailureMode(SimAnalysis): diff --git a/PyLTSpice/sim/tookit/montecarlo.py b/PyLTSpice/sim/tookit/montecarlo.py new file mode 100644 index 0000000..fb9e2a1 --- /dev/null +++ b/PyLTSpice/sim/tookit/montecarlo.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python +# coding=utf-8 + +# ------------------------------------------------------------------------------- +# ____ _ _____ ____ _ +# | _ \ _ _| | |_ _/ ___| _ __ (_) ___ ___ +# | |_) | | | | | | | \___ \| '_ \| |/ __/ _ \ +# | __/| |_| | |___| | ___) | |_) | | (_| __/ +# |_| \__, |_____|_| |____/| .__/|_|\___\___| +# |___/ |_| +# +# Name: montecarlo.py +# Purpose: Classes to automate Monte-Carlo simulations +# +# Author: Nuno Brum (nuno.brum@gmail.com) +# +# Created: 10-08-2023 +# Licence: refer to the LICENSE file +# ------------------------------------------------------------------------------- \ No newline at end of file diff --git a/PyLTSpice/sim/tookit/sim_analysis.py b/PyLTSpice/sim/tookit/sim_analysis.py new file mode 100644 index 0000000..77e1a6c --- /dev/null +++ b/PyLTSpice/sim/tookit/sim_analysis.py @@ -0,0 +1,56 @@ +#!/usr/bin/env python +# coding=utf-8 + +# ------------------------------------------------------------------------------- +# ____ _ _____ ____ _ +# | _ \ _ _| | |_ _/ ___| _ __ (_) ___ ___ +# | |_) | | | | | | | \___ \| '_ \| |/ __/ _ \ +# | __/| |_| | |___| | ___) | |_) | | (_| __/ +# |_| \__, |_____|_| |____/| .__/|_|\___\___| +# |___/ |_| +# +# Name: sim_analysis.py +# Purpose: Classes to automate Monte-Carlo, FMEA or Worst Case Analysis +# be updated by user instructions +# +# Author: Nuno Brum (nuno.brum@gmail.com) +# +# Created: 06-07-2021 +# Licence: refer to the LICENSE file +# ------------------------------------------------------------------------------- + +from collections import OrderedDict +from typing import Union, Optional + +from ...sim.sim_runner import AnyRunner +from ...editor.base_editor import BaseEditor +from ...sim.simulator import Simulator + + +class SimAnalysis(object): + """ + Base class for making Monte-Carlo, Extreme Value Analysis (EVA) or Failure Mode and Effects Analysis. + As a base class, a certain number of assertions must be made on the simulation results that will make the pass/fail. + + Note: For the time being only measurements done with .MEAS are possible. At a later stage the parsing of RAW files + will be possible, although, it seems that the later solution is less computing intense. + """ + + def __init__(self, circuit_file: Union[str, BaseEditor], simulator: Optional[Simulator] = None, + runner: Optional[AnyRunner] = None): + if isinstance(circuit_file, str): + from ..editor.spice_editor import SpiceEditor + self.editor = SpiceEditor(circuit_file) + else: + self.editor = circuit_file + if simulator is None: + from ..sim.ltspice_simulator import LTspice + self.simulator = LTspice() + else: + self.simulator = simulator + if runner is None: + from ..sim.sim_runner import SimRunner + self.runner = SimRunner(parallel_sims=1, timeout=None, verbose=False, output_folder=None) + self.simulations = OrderedDict() + + diff --git a/doc/classes/SpiceCircuit.rst b/doc/classes/SpiceCircuit.rst deleted file mode 100644 index 8dad2fe..0000000 --- a/doc/classes/SpiceCircuit.rst +++ /dev/null @@ -1,7 +0,0 @@ -SpiceCircuit -============ - -.. autoclass:: PyLTSpice.SpiceEditor.SpiceCircuit - :members: - :undoc-members: - :show-inheritance: \ No newline at end of file diff --git a/doc/classes/SpiceEditor.rst b/doc/classes/SpiceEditor.rst deleted file mode 100644 index a2a074c..0000000 --- a/doc/classes/SpiceEditor.rst +++ /dev/null @@ -1,7 +0,0 @@ -SpiceEditor -=========== - -.. autoclass:: PyLTSpice.SpiceEditor.SpiceEditor - :members: - :undoc-members: - :show-inheritance: \ No newline at end of file diff --git a/doc/classes/asc_editor.rst b/doc/classes/asc_editor.rst new file mode 100644 index 0000000..74d5a33 --- /dev/null +++ b/doc/classes/asc_editor.rst @@ -0,0 +1,9 @@ +AscEditor +============ + +Class used for manipulating LTSpice asc files. + +.. autoclass:: PyLTSpice.editor.asc_editor.AscEditor + :members: + :undoc-members: + :show-inheritance: diff --git a/doc/classes/editor_classes.rst b/doc/classes/editor_classes.rst new file mode 100644 index 0000000..b09237f --- /dev/null +++ b/doc/classes/editor_classes.rst @@ -0,0 +1,9 @@ +Editor Classes +============== + +.. toctree:: + :maxdepth: 4 + + spice_editor + spice_circuit + asc_editor diff --git a/doc/classes/raw_classes.rst b/doc/classes/raw_classes.rst new file mode 100644 index 0000000..56d5f32 --- /dev/null +++ b/doc/classes/raw_classes.rst @@ -0,0 +1,13 @@ +======================== +Raw and Log File Classes +======================== + +.. toctree:: + :maxdepth: 4 + + raw_read + trace + logreader + raw_write + write_trace + \ No newline at end of file diff --git a/doc/classes/sim_client.rst b/doc/classes/sim_client.rst index df5a334..201d1f0 100644 --- a/doc/classes/sim_client.rst +++ b/doc/classes/sim_client.rst @@ -1,5 +1,6 @@ -SimClient (Under development) -============================= +========= +SimClient +========= .. autoclass:: PyLTSpice.client_server.sim_client.SimClient :members: diff --git a/doc/classes/sim_server.rst b/doc/classes/sim_server.rst index 6437793..07c891a 100644 --- a/doc/classes/sim_server.rst +++ b/doc/classes/sim_server.rst @@ -1,5 +1,6 @@ -SimServer (Under development) -============================= +========= +SimServer +========= .. autoclass:: PyLTSpice.client_server.sim_server.SimServer :members: diff --git a/doc/classes/classes.rst b/doc/classes/simulation_classes.rst similarity index 62% rename from doc/classes/classes.rst rename to doc/classes/simulation_classes.rst index e62b24b..82a3006 100644 --- a/doc/classes/classes.rst +++ b/doc/classes/simulation_classes.rst @@ -1,16 +1,11 @@ -============== -Python Classes -============== - +================== +Simulation Classes +================== .. toctree:: :maxdepth: 4 - - spice_editor - spice_circuit + sim_runner sim_simulator - raw_read - raw_write sim_client sim_server diff --git a/doc/classes/spice_circuit.rst b/doc/classes/spice_circuit.rst index 4effc3c..a3217d5 100644 --- a/doc/classes/spice_circuit.rst +++ b/doc/classes/spice_circuit.rst @@ -1,7 +1,7 @@ SpiceCircuit ============ -.. autoclass:: PyLTSpice.sim.spice_editor.SpiceCircuit +.. autoclass:: PyLTSpice.editor.spice_editor.SpiceCircuit :members: :undoc-members: :show-inheritance: \ No newline at end of file diff --git a/doc/classes/spice_editor.rst b/doc/classes/spice_editor.rst index f7e4027..c3a2b0d 100644 --- a/doc/classes/spice_editor.rst +++ b/doc/classes/spice_editor.rst @@ -3,7 +3,7 @@ SpiceEditor Class used for manipulating SPICE netlists. Inherits from SpiceCircuit. -.. autoclass:: PyLTSpice.sim.spice_editor.SpiceEditor +.. autoclass:: PyLTSpice.editor.spice_editor.SpiceEditor :members: :undoc-members: :show-inheritance: diff --git a/doc/classes/trace.rst b/doc/classes/trace.rst index 8d0c654..b0aed41 100644 --- a/doc/classes/trace.rst +++ b/doc/classes/trace.rst @@ -1,7 +1,12 @@ RawRead Trace ============= -.. autoclass:: PyLTSpice.raw_classes.Trace +.. autoclass:: PyLTSpice.raw.raw_classes.Axis + :members: + :undoc-members: + :show-inheritance: + +.. autoclass:: PyLTSpice.raw.raw_classes.TraceRead :members: :undoc-members: :show-inheritance: \ No newline at end of file diff --git a/doc/classes/write_trace.rst b/doc/classes/write_trace.rst index 1ec54d5..9bd4e9d 100644 --- a/doc/classes/write_trace.rst +++ b/doc/classes/write_trace.rst @@ -1,7 +1,7 @@ RawWrite Trace ============== -.. autoclass:: PyLTSpice.raw_write.Trace +.. autoclass:: PyLTSpice.raw.raw_write.Trace :members: :undoc-members: :show-inheritance: \ No newline at end of file