diff --git a/core/commit_stage.sv b/core/commit_stage.sv index 17635ddc6a..1b67179d2f 100644 --- a/core/commit_stage.sv +++ b/core/commit_stage.sv @@ -103,7 +103,7 @@ module commit_stage // ); for (genvar i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin : gen_waddr - assign waddr_o[i] = commit_instr_i[i].rd[4:0]; + assign waddr_o[i] = commit_instr_i[i].rd; end assign pc_o = commit_instr_i[0].pc; diff --git a/core/cva6_rvfi.sv b/core/cva6_rvfi.sv index 671995c634..83e197e0c5 100644 --- a/core/cva6_rvfi.sv +++ b/core/cva6_rvfi.sv @@ -301,9 +301,9 @@ module cva6_rvfi rvfi_instr_o[i].cause <= ex_commit_cause; rvfi_instr_o[i].mode <= (CVA6Cfg.DebugEn && debug_mode) ? 2'b10 : priv_lvl; rvfi_instr_o[i].ixl <= CVA6Cfg.XLEN == 64 ? 2 : 1; - rvfi_instr_o[i].rs1_addr <= commit_instr_rs1[i][4:0]; - rvfi_instr_o[i].rs2_addr <= commit_instr_rs2[i][4:0]; - rvfi_instr_o[i].rd_addr <= commit_instr_rd[i][4:0]; + rvfi_instr_o[i].rs1_addr <= commit_instr_rs1[i]; + rvfi_instr_o[i].rs2_addr <= commit_instr_rs2[i]; + rvfi_instr_o[i].rd_addr <= commit_instr_rd[i]; rvfi_instr_o[i].rd_wdata <= (CVA6Cfg.FpPresent && is_rd_fpr( commit_instr_op[i] )) ? commit_instr_result[i] : wdata[i]; diff --git a/core/decoder.sv b/core/decoder.sv index 5f30ac8880..03f44f0ca8 100644 --- a/core/decoder.sv +++ b/core/decoder.sv @@ -188,9 +188,9 @@ module decoder case (instr.rtype.opcode) riscv::OpcodeSystem: begin instruction_o.fu = CSR; - instruction_o.rs1[4:0] = instr.itype.rs1; - instruction_o.rs2[4:0] = instr.rtype.rs2; //TODO: needs to be checked if better way is available - instruction_o.rd[4:0] = instr.itype.rd; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rs2 = instr.rtype.rs2; //TODO: needs to be checked if better way is available + instruction_o.rd = instr.itype.rd; unique case (instr.itype.funct3) 3'b000: begin @@ -329,13 +329,13 @@ module decoder if (instr.instr[25] != 1'b0) begin instruction_o.fu = STORE; imm_select = NOIMM; - instruction_o.rs1[4:0] = instr.stype.rs1; - instruction_o.rs2[4:0] = instr.stype.rs2; + instruction_o.rs1 = instr.stype.rs1; + instruction_o.rs2 = instr.stype.rs2; end else begin instruction_o.fu = LOAD; imm_select = NOIMM; - instruction_o.rs1[4:0] = instr.itype.rs1; - instruction_o.rd[4:0] = instr.itype.rd; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rd = instr.itype.rd; end // Hypervisor load/store instructions when V=1 cause virtual instruction @@ -402,25 +402,25 @@ module decoder 3'b010: begin // CSRRS imm_select = IIMM; // this is just a read - if (instr.itype.rs1 == 5'b0) instruction_o.op = ariane_pkg::CSR_READ; + if (instr.itype.rs1 == '0) instruction_o.op = ariane_pkg::CSR_READ; else instruction_o.op = ariane_pkg::CSR_SET; end // atomically clear values in the CSR and write back to rd 3'b011: begin // CSRRC imm_select = IIMM; // this is just a read - if (instr.itype.rs1 == 5'b0) instruction_o.op = ariane_pkg::CSR_READ; + if (instr.itype.rs1 == '0) instruction_o.op = ariane_pkg::CSR_READ; else instruction_o.op = ariane_pkg::CSR_CLEAR; end // use zimm and iimm 3'b101: begin // CSRRWI - instruction_o.rs1[4:0] = instr.itype.rs1; + instruction_o.rs1 = instr.itype.rs1; imm_select = IIMM; instruction_o.use_zimm = 1'b1; instruction_o.op = ariane_pkg::CSR_WRITE; end 3'b110: begin // CSRRSI - instruction_o.rs1[4:0] = instr.itype.rs1; + instruction_o.rs1 = instr.itype.rs1; imm_select = IIMM; instruction_o.use_zimm = 1'b1; // this is just a read @@ -428,11 +428,11 @@ module decoder else instruction_o.op = ariane_pkg::CSR_SET; end 3'b111: begin // CSRRCI - instruction_o.rs1[4:0] = instr.itype.rs1; + instruction_o.rs1 = instr.itype.rs1; imm_select = IIMM; instruction_o.use_zimm = 1'b1; // this is just a read - if (instr.itype.rs1 == 5'b0) instruction_o.op = ariane_pkg::CSR_READ; + if (instr.itype.rs1 == '0) instruction_o.op = ariane_pkg::CSR_READ; else instruction_o.op = ariane_pkg::CSR_CLEAR; end default: illegal_instr = 1'b1; @@ -468,24 +468,24 @@ module decoder if (CVA6Cfg.FpPresent && CVA6Cfg.XFVec && fs_i != riscv::Off && ((CVA6Cfg.RVH && (!v_i || vfs_i != riscv::Off)) || !CVA6Cfg.RVH)) begin automatic logic allow_replication; // control honoring of replication flag - instruction_o.fu = FPU_VEC; // Same unit, but sets 'vectorial' signal - instruction_o.rs1[4:0] = instr.rvftype.rs1; - instruction_o.rs2[4:0] = instr.rvftype.rs2; - instruction_o.rd[4:0] = instr.rvftype.rd; - check_fprm = 1'b1; - allow_replication = 1'b1; + instruction_o.fu = FPU_VEC; // Same unit, but sets 'vectorial' signal + instruction_o.rs1 = instr.rvftype.rs1; + instruction_o.rs2 = instr.rvftype.rs2; + instruction_o.rd = instr.rvftype.rd; + check_fprm = 1'b1; + allow_replication = 1'b1; // decode vectorial FP instruction unique case (instr.rvftype.vecfltop) 5'b00001: begin - instruction_o.op = ariane_pkg::FADD; // vfadd.vfmt - Vectorial FP Addition - instruction_o.rs1 = '0; // Operand A is set to 0 - instruction_o.rs2[4:0] = instr.rvftype.rs1; // Operand B is set to rs1 - imm_select = IIMM; // Operand C is set to rs2 + instruction_o.op = ariane_pkg::FADD; // vfadd.vfmt - Vectorial FP Addition + instruction_o.rs1 = '0; // Operand A is set to 0 + instruction_o.rs2 = instr.rvftype.rs1; // Operand B is set to rs1 + imm_select = IIMM; // Operand C is set to rs2 end 5'b00010: begin instruction_o.op = ariane_pkg::FSUB; // vfsub.vfmt - Vectorial FP Subtraction instruction_o.rs1 = '0; // Operand A is set to 0 - instruction_o.rs2[4:0] = instr.rvftype.rs1; // Operand B is set to rs1 + instruction_o.rs2 = instr.rvftype.rs1; // Operand B is set to rs1 imm_select = IIMM; // Operand C is set to rs2 end 5'b00011: @@ -516,7 +516,7 @@ module decoder 5'b01100: begin unique case (instr.rvftype.rs2) inside // operation encoded in rs2, `inside` for matching ? 5'b00000: begin - instruction_o.rs2[4:0] = instr.rvftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit + instruction_o.rs2 = instr.rvftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit if (instr.rvftype.repl) instruction_o.op = ariane_pkg::FMV_X2F; // vfmv.vfmt.x - GPR to FPR Move else instruction_o.op = ariane_pkg::FMV_F2X; // vfmv.x.vfmt - FPR to GPR Move @@ -533,7 +533,7 @@ module decoder instruction_o.op = ariane_pkg::FCVT_I2F; // vfcvt.vfmt.x - Vectorial Int to FP Conversion 5'b001??: begin instruction_o.op = ariane_pkg::FCVT_F2F; // vfcvt.vfmt.vfmt - Vectorial FP to FP Conversion - instruction_o.rs2[4:0] = instr.rvftype.rd; // set rs2 = rd as target vector for conversion + instruction_o.rs2 = instr.rvftype.rd; // set rs2 = rd as target vector for conversion imm_select = IIMM; // rs2 holds part of the intruction // TODO CHECK R bit for valid fmt combinations // determine source format @@ -716,9 +716,9 @@ module decoder end else begin instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU; end - instruction_o.rs1[4:0] = instr.rtype.rs1; - instruction_o.rs2[4:0] = instr.rtype.rs2; - instruction_o.rd[4:0] = instr.rtype.rd; + instruction_o.rs1 = instr.rtype.rs1; + instruction_o.rs2 = instr.rtype.rs2; + instruction_o.rd = instr.rtype.rd; unique case ({ instr.rtype.funct7, instr.rtype.funct3 @@ -819,10 +819,10 @@ module decoder // 32bit Reg-Reg Operations // -------------------------- riscv::OpcodeOp32: begin - instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU; - instruction_o.rs1[4:0] = instr.rtype.rs1; - instruction_o.rs2[4:0] = instr.rtype.rs2; - instruction_o.rd[4:0] = instr.rtype.rd; + instruction_o.fu = (instr.rtype.funct7 == 7'b000_0001) ? MULT : ALU; + instruction_o.rs1 = instr.rtype.rs1; + instruction_o.rs2 = instr.rtype.rs2; + instruction_o.rd = instr.rtype.rd; if (CVA6Cfg.IS_XLEN64) begin unique case ({ instr.rtype.funct7, instr.rtype.funct3 @@ -875,8 +875,8 @@ module decoder riscv::OpcodeOpImm: begin instruction_o.fu = ALU; imm_select = IIMM; - instruction_o.rs1[4:0] = instr.itype.rs1; - instruction_o.rd[4:0] = instr.itype.rd; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rd = instr.itype.rd; unique case (instr.itype.funct3) 3'b000: instruction_o.op = ariane_pkg::ADD; // Add Immediate 3'b010: instruction_o.op = ariane_pkg::SLTS; // Set to one if Lower Than Immediate @@ -940,8 +940,8 @@ module decoder riscv::OpcodeOpImm32: begin instruction_o.fu = ALU; imm_select = IIMM; - instruction_o.rs1[4:0] = instr.itype.rs1; - instruction_o.rd[4:0] = instr.itype.rd; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rd = instr.itype.rd; if (CVA6Cfg.IS_XLEN64) begin unique case (instr.itype.funct3) 3'b000: instruction_o.op = ariane_pkg::ADDW; // Add Immediate @@ -989,8 +989,8 @@ module decoder riscv::OpcodeStore: begin instruction_o.fu = STORE; imm_select = SIMM; - instruction_o.rs1[4:0] = instr.stype.rs1; - instruction_o.rs2[4:0] = instr.stype.rs2; + instruction_o.rs1 = instr.stype.rs1; + instruction_o.rs2 = instr.stype.rs2; // determine store size unique case (instr.stype.funct3) 3'b000: instruction_o.op = ariane_pkg::SB; @@ -1010,8 +1010,8 @@ module decoder riscv::OpcodeLoad: begin instruction_o.fu = LOAD; imm_select = IIMM; - instruction_o.rs1[4:0] = instr.itype.rs1; - instruction_o.rd[4:0] = instr.itype.rd; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rd = instr.itype.rd; // determine load size and signed type unique case (instr.itype.funct3) 3'b000: instruction_o.op = ariane_pkg::LB; @@ -1040,8 +1040,8 @@ module decoder if (CVA6Cfg.FpPresent && fs_i != riscv::Off && ((CVA6Cfg.RVH && (!v_i || vfs_i != riscv::Off)) || !CVA6Cfg.RVH)) begin // only generate decoder if FP extensions are enabled (static) instruction_o.fu = STORE; imm_select = SIMM; - instruction_o.rs1[4:0] = instr.stype.rs1; - instruction_o.rs2[4:0] = instr.stype.rs2; + instruction_o.rs1 = instr.stype.rs1; + instruction_o.rs2 = instr.stype.rs2; // determine store size unique case (instr.stype.funct3) // Only process instruction if corresponding extension is active (static) @@ -1070,8 +1070,8 @@ module decoder if (CVA6Cfg.FpPresent && fs_i != riscv::Off && ((CVA6Cfg.RVH && (!v_i || vfs_i != riscv::Off)) || !CVA6Cfg.RVH)) begin // only generate decoder if FP extensions are enabled (static) instruction_o.fu = LOAD; imm_select = IIMM; - instruction_o.rs1[4:0] = instr.itype.rs1; - instruction_o.rd[4:0] = instr.itype.rd; + instruction_o.rs1 = instr.itype.rs1; + instruction_o.rd = instr.itype.rd; // determine load size unique case (instr.itype.funct3) // Only process instruction if corresponding extension is active (static) @@ -1101,12 +1101,12 @@ module decoder // ---------------------------------- riscv::OpcodeMadd, riscv::OpcodeMsub, riscv::OpcodeNmsub, riscv::OpcodeNmadd: begin if (CVA6Cfg.FpPresent && fs_i != riscv::Off && ((CVA6Cfg.RVH && (!v_i || vfs_i != riscv::Off)) || !CVA6Cfg.RVH)) begin // only generate decoder if FP extensions are enabled (static) - instruction_o.fu = FPU; - instruction_o.rs1[4:0] = instr.r4type.rs1; - instruction_o.rs2[4:0] = instr.r4type.rs2; - instruction_o.rd[4:0] = instr.r4type.rd; - imm_select = RS3; // rs3 into result field - check_fprm = 1'b1; + instruction_o.fu = FPU; + instruction_o.rs1 = instr.r4type.rs1; + instruction_o.rs2 = instr.r4type.rs2; + instruction_o.rd = instr.r4type.rd; + imm_select = RS3; // rs3 into result field + check_fprm = 1'b1; // select the correct fused operation unique case (instr.r4type.opcode) default: instruction_o.op = ariane_pkg::FMADD; // fmadd.fmt - FP Fused multiply-add @@ -1156,24 +1156,24 @@ module decoder riscv::OpcodeOpFp: begin if (CVA6Cfg.FpPresent && fs_i != riscv::Off && ((CVA6Cfg.RVH && (!v_i || vfs_i != riscv::Off)) || !CVA6Cfg.RVH)) begin // only generate decoder if FP extensions are enabled (static) - instruction_o.fu = FPU; - instruction_o.rs1[4:0] = instr.rftype.rs1; - instruction_o.rs2[4:0] = instr.rftype.rs2; - instruction_o.rd[4:0] = instr.rftype.rd; - check_fprm = 1'b1; + instruction_o.fu = FPU; + instruction_o.rs1 = instr.rftype.rs1; + instruction_o.rs2 = instr.rftype.rs2; + instruction_o.rd = instr.rftype.rd; + check_fprm = 1'b1; // decode FP instruction unique case (instr.rftype.funct5) 5'b00000: begin - instruction_o.op = ariane_pkg::FADD; // fadd.fmt - FP Addition - instruction_o.rs1 = '0; // Operand A is set to 0 - instruction_o.rs2[4:0] = instr.rftype.rs1; // Operand B is set to rs1 - imm_select = IIMM; // Operand C is set to rs2 + instruction_o.op = ariane_pkg::FADD; // fadd.fmt - FP Addition + instruction_o.rs1 = '0; // Operand A is set to 0 + instruction_o.rs2 = instr.rftype.rs1; // Operand B is set to rs1 + imm_select = IIMM; // Operand C is set to rs2 end 5'b00001: begin - instruction_o.op = ariane_pkg::FSUB; // fsub.fmt - FP Subtraction - instruction_o.rs1 = '0; // Operand A is set to 0 - instruction_o.rs2[4:0] = instr.rftype.rs1; // Operand B is set to rs1 - imm_select = IIMM; // Operand C is set to rs2 + instruction_o.op = ariane_pkg::FSUB; // fsub.fmt - FP Subtraction + instruction_o.rs1 = '0; // Operand A is set to 0 + instruction_o.rs2 = instr.rftype.rs1; // Operand B is set to rs1 + imm_select = IIMM; // Operand C is set to rs2 end 5'b00010: instruction_o.op = ariane_pkg::FMUL; // fmul.fmt - FP Multiplication 5'b00011: instruction_o.op = ariane_pkg::FDIV; // fdiv.fmt - FP Division @@ -1204,7 +1204,7 @@ module decoder end 5'b01000: begin instruction_o.op = ariane_pkg::FCVT_F2F; // fcvt.fmt.fmt - FP to FP Conversion - instruction_o.rs2[4:0] = instr.rvftype.rs1; // tie rs2 to rs1 to be safe (vectors use rs2) + instruction_o.rs2 = instr.rvftype.rs1; // tie rs2 to rs1 to be safe (vectors use rs2) imm_select = IIMM; // rs2 holds part of the intruction if (|instr.rftype.rs2[24:23]) illegal_instr = 1'b1; // bits [22:20] used, other bits must be 0 @@ -1242,7 +1242,7 @@ module decoder illegal_instr = 1'b1; // bits [21:20] used, other bits must be 0 end 5'b11100: begin - instruction_o.rs2[4:0] = instr.rftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit + instruction_o.rs2 = instr.rftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit check_fprm = 1'b0; // instruction encoded in rm, do the check here if (instr.rftype.rm == 3'b000 || (CVA6Cfg.XF16ALT && instr.rftype.rm == 3'b100)) // FP16ALT has separate encoding instruction_o.op = ariane_pkg::FMV_F2X; // fmv.ifmt.fmt - FPR to GPR Move @@ -1254,7 +1254,7 @@ module decoder end 5'b11110: begin instruction_o.op = ariane_pkg::FMV_X2F; // fmv.fmt.ifmt - GPR to FPR Move - instruction_o.rs2[4:0] = instr.rftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit + instruction_o.rs2 = instr.rftype.rs1; // set rs2 = rs1 so we can map FMV to SGNJ in the unit check_fprm = 1'b0; // instruction encoded in rm, do the check here if (!(instr.rftype.rm == 3'b000 || (CVA6Cfg.XF16ALT && instr.rftype.rm == 3'b100))) illegal_instr = 1'b1; @@ -1305,10 +1305,10 @@ module decoder // ---------------------------------- riscv::OpcodeAmo: begin // we are going to use the load unit for AMOs - instruction_o.fu = STORE; - instruction_o.rs1[4:0] = instr.atype.rs1; - instruction_o.rs2[4:0] = instr.atype.rs2; - instruction_o.rd[4:0] = instr.atype.rd; + instruction_o.fu = STORE; + instruction_o.rs1 = instr.atype.rs1; + instruction_o.rs2 = instr.atype.rs2; + instruction_o.rd = instr.atype.rd; // TODO(zarubaf): Ordering // words if (CVA6Cfg.RVA && instr.stype.funct3 == 3'h2) begin @@ -1369,8 +1369,8 @@ module decoder riscv::OpcodeBranch: begin imm_select = SBIMM; instruction_o.fu = CTRL_FLOW; - instruction_o.rs1[4:0] = instr.stype.rs1; - instruction_o.rs2[4:0] = instr.stype.rs2; + instruction_o.rs1 = instr.stype.rs1; + instruction_o.rs2 = instr.stype.rs2; is_control_flow_instr_o = 1'b1; @@ -1391,9 +1391,9 @@ module decoder riscv::OpcodeJalr: begin instruction_o.fu = CTRL_FLOW; instruction_o.op = ariane_pkg::JALR; - instruction_o.rs1[4:0] = instr.itype.rs1; + instruction_o.rs1 = instr.itype.rs1; imm_select = IIMM; - instruction_o.rd[4:0] = instr.itype.rd; + instruction_o.rd = instr.itype.rd; is_control_flow_instr_o = 1'b1; // invalid jump and link register -> reserved for vector encoding if (instr.itype.funct3 != 3'b0) illegal_instr = 1'b1; @@ -1402,21 +1402,21 @@ module decoder riscv::OpcodeJal: begin instruction_o.fu = CTRL_FLOW; imm_select = JIMM; - instruction_o.rd[4:0] = instr.utype.rd; + instruction_o.rd = instr.utype.rd; is_control_flow_instr_o = 1'b1; end riscv::OpcodeAuipc: begin - instruction_o.fu = ALU; - imm_select = UIMM; - instruction_o.use_pc = 1'b1; - instruction_o.rd[4:0] = instr.utype.rd; + instruction_o.fu = ALU; + imm_select = UIMM; + instruction_o.use_pc = 1'b1; + instruction_o.rd = instr.utype.rd; end riscv::OpcodeLui: begin - imm_select = UIMM; - instruction_o.fu = ALU; - instruction_o.rd[4:0] = instr.utype.rd; + imm_select = UIMM; + instruction_o.fu = ALU; + instruction_o.rd = instr.utype.rd; end default: illegal_instr = 1'b1; @@ -1425,9 +1425,9 @@ module decoder if (CVA6Cfg.CvxifEn) begin if (~ex_i.valid && (is_illegal_i || illegal_instr)) begin instruction_o.fu = CVXIF; - instruction_o.rs1[4:0] = instr.r4type.rs1; - instruction_o.rs2[4:0] = instr.r4type.rs2; - instruction_o.rd[4:0] = instr.r4type.rd; + instruction_o.rs1 = instr.r4type.rs1; + instruction_o.rs2 = instr.r4type.rs2; + instruction_o.rd = instr.r4type.rd; instruction_o.op = ariane_pkg::OFFLOAD; imm_select = instr.rtype.opcode == riscv::OpcodeMadd || instr.rtype.opcode == riscv::OpcodeMsub || diff --git a/core/issue_read_operands.sv b/core/issue_read_operands.sv index 1666de5c70..c54fec41ee 100644 --- a/core/issue_read_operands.sv +++ b/core/issue_read_operands.sv @@ -696,13 +696,13 @@ module issue_read_operands for (int unsigned c = 0; c < CVA6Cfg.NrCommitPorts; c++) begin if ((CVA6Cfg.FpPresent && ariane_pkg::is_rd_fpr( issue_instr_i[i].op - )) ? (we_fpr_i[c] && waddr_i[c] == issue_instr_i[i].rd[4:0]) : - (we_gpr_i[c] && waddr_i[c] == issue_instr_i[i].rd[4:0])) begin + )) ? (we_fpr_i[c] && waddr_i[c] == issue_instr_i[i].rd) : + (we_gpr_i[c] && waddr_i[c] == issue_instr_i[i].rd)) begin stall_waw[i] = 1'b0; end end if (i > 0) begin - if ((issue_instr_i[i].rd[4:0] == issue_instr_i[i-1].rd[4:0]) && (issue_instr_i[i].rd[4:0] != '0)) begin + if ((issue_instr_i[i].rd == issue_instr_i[i-1].rd) && (issue_instr_i[i].rd != '0)) begin stall_waw[i] = 1'b1; end end @@ -761,8 +761,8 @@ module issue_read_operands logic [CVA6Cfg.NrCommitPorts-1:0] we_pack; for (genvar i = 0; i < CVA6Cfg.NrIssuePorts; i++) begin - assign raddr_pack[i*OPERANDS_PER_INSTR+0] = issue_instr_i[i].rs1[4:0]; - assign raddr_pack[i*OPERANDS_PER_INSTR+1] = issue_instr_i[i].rs2[4:0]; + assign raddr_pack[i*OPERANDS_PER_INSTR+0] = issue_instr_i[i].rs1; + assign raddr_pack[i*OPERANDS_PER_INSTR+1] = issue_instr_i[i].rs2; if (OPERANDS_PER_INSTR == 3) begin assign raddr_pack[i*OPERANDS_PER_INSTR+2] = issue_instr_i[i].result[4:0]; end diff --git a/core/store_unit.sv b/core/store_unit.sv index 9b85180f68..d000623a25 100644 --- a/core/store_unit.sv +++ b/core/store_unit.sv @@ -89,7 +89,7 @@ module store_unit // align data to address e.g.: shift data to be naturally 64 function automatic [CVA6Cfg.XLEN-1:0] data_align(logic [2:0] addr, logic [63:0] data); // Set addr[2] to 1'b0 when 32bits - logic [2:0] addr_tmp = {(addr[2] && CVA6Cfg.IS_XLEN64), addr[1:0]}; + logic [ 2:0] addr_tmp = {(addr[2] && CVA6Cfg.IS_XLEN64), addr[1:0]}; logic [63:0] data_tmp = {64{1'b0}}; case (addr_tmp) 3'b000: data_tmp[CVA6Cfg.XLEN-1:0] = {data[CVA6Cfg.XLEN-1:0]};