Using DMA between Two State Machines, RP2040 Pico #15958

sk8board · 2024-10-03T12:58:10Z

sk8board
Oct 3, 2024

I am trying to use a DMA channel to move data from one state machine to the next state machine, but I am having trouble getting the DMA channel to function.

I have created two simple state machines which function as intended.

Could you please help by showing my error with DMA?

# RP2040 Pico

# Expected result: single bits are fed to state machine 0, 
# then DMA moves RX FIFO of state machine 0 to TX FIFO state machine 1, 
# then state machine 1 builds a 32-bit array one bit at a time.

# Actual result: DMA does not function as intended

import time
from rp2 import PIO, asm_pio, StateMachine

### State Machine 0
@rp2.asm_pio(in_shiftdir=0, out_shiftdir=1, autopull=True, pull_thresh=1, autopush=True, push_thresh=1)
def bounce():       # move a single bit from TX FIFO to RX FIFO
    wrap_target()

    out(x, 1)       # shift in one bit from OSR to scratch x
    in_(x, 1)       # shift out one bit from scratch x to ISR
    irq(rel(0))
    
    wrap()

def sm0_handler(sm0):
    print("sm0", sm0.get())

sm0 = rp2.StateMachine(0, bounce)
#sm0.irq(sm0_handler)   # uncomment to debug sm0
sm0.active(1)

### State Machine 1
@rp2.asm_pio(in_shiftdir=0, out_shiftdir=1, autopull=True, pull_thresh=1, autopush=True, push_thresh=32) # set the bit order direction of OSR and ISR as well as autopull threshold to allow a single bit into the state machine while storing these bits in the ISR until full (32-bits) 
def build_bitstream():  # accumulate 32-bits to the RX FIFO one bit at a time from the TX FIFO
    wrap_target()

    set(y, 31)			# set scratch y to 31, this will count down for each bit to be added to ISR

    label("loop")
    pull(block)			# wait (block) for a 32-bit word to be added to the TX FIFO, then move the word to the OSR
    out(x, 1)			# move one bit from OSR to scratch x
    in_(x, 1)			# move one bit from scratch x to ISR
    jmp(y_dec, "loop")	# loop back unill 32 bits (bit stream) have filled the ISR
    
    irq(rel(0))			# set IRQ flag which will trigger the IRQ handler to get the 32-bit word from the RX FIFO
    wrap()

def sm1_handler(sm1):
    SM1_RX_FIFO_Receive = sm1.get()
    print(bin(SM1_RX_FIFO_Receive))
    print("SM1_RX_FIFO_Receive")

sm1 = rp2.StateMachine(1, build_bitstream)	# build array of bit at clock speed
sm1.irq(sm1_handler, trigger=1, hard=False)
sm1.active(1)	# Start state machine


### DMA 0
RXF0_addr = const(0x50200020)   # address of RX FIFO register for State Machine 0
TXF1_addr = const(0x50200014)   # address of TX FIFO register for State Machine 1

dma0 = rp2.DMA()
dma0_ctrl = dma0.pack_ctrl(
    enable = True,           # enable DMA channel
    high_pri = True,        # set DMA bus traffic priority as high
    size = 2,                   # Transfer size: 0=byte, 1=half word, 2=word (default: 2)
    inc_read = False,       # do not increment to read address
    inc_write = False,      # do not increment the write address
    ring_size = 0,           # increment size is zero
    ring_sel = False,        # use ring_size
    treq_sel = 1,             # select transfer rate of PIO0 TX FIFO, DREQ_PIO0_TX1
    irq_quiet = True,       # do not generate an interrupt after transfer is complete
    bswap = False,          # do not reverse the order of the word
    sniff_en = False         # do not allow access to debug
)

dma0_config = dma0.config(read=RXF0_addr, write=TXF1_addr, count=1, ctrl=dma0_ctrl, trigger=True)
dma0.active(1)


test_bitstream = 0b1111111111010100100101100010111000

# bit shift function
def get_bit(value, n):
    return ((value >> n & 1) != 0)

# write test_bitstream one bit at a time to state machine 0
for k in range(0, 4):
    for i in range(31,-1,-1):
        j = get_bit(test_bitstream, i)
        if j == 1:
            sm0.put(0b1)
        if j == 0:
            sm0.put(0b0)
        time.sleep_us(100)

time.sleep(1)
sm0.active(0)
sm1.active(0)
dma0.active(0)
machine.soft_reset()

Answered by sk8board

Oct 9, 2024

I rewrote my DMA interrupt example with Viper and the use of pointers showed how to use DMA the chaining ping-pong method. I created a demo of it here.

View full answer

bidrohini · 2024-10-03T14:25:55Z

bidrohini
Oct 3, 2024

The state machine and DMA controller should be synchronized correctly. If the state machine is not producing data fast enough, or if there is a delay between transfers, the DMA may not behave as expected. Try to add some status checking or debug printouts to verify if the FIFO contents are being consumed correctly.

1 reply

sk8board Oct 3, 2024
Author

Thank you for your reply.

State machine 0 (sm0) TX FIFO should be written to every 100 microseconds.

I need DMA to transfer the contents of sm0 RX FIFO to sm1 TX FIFO after being triggered by a write to sm0 RX FIFO.

Based on my debug printouts, DMA is not being triggered once sm0 TX FIFO has been written to. This appears to be a trigger problem. But where is the problem?

sk8board · 2024-10-03T22:51:34Z

sk8board
Oct 3, 2024
Author

I dug into the RP2040 Datasheet and found I have to use the state machine interrupt to call a function which sets the DMA trigger bit to 1 every time the RX FIFO is ready for data to be transferred to the next state machine.

Here is a typical MicroPython memory function that can be used to change a bit to the DMA register.

def trigger_DMA(sm0):
    machine.mem32[0x50000430] |= 0b00001  # triggers DMA chan0, reference 2.5.7 of the RP2040 Datasheet for DMA: MULTI_CHAN_TRIGGER Register

Then set state machine 0 interrupt as follows:

sm0.irq(trigger_DMA) # Trigger DMA channel 0 to move data from sm0 RX FIFO to sm1 TX FIFO

While this does cause the DMA to transfer data, the MicroPython code is too slow and causes some of the bits to be dropped on the next interrupt call.

Therefore, I had to use Viper code, which is faster.

# RP2040 Pico demo of DMA use between state machines

# Expected result:
# 1) single bits are fed to state machine 0, 
# 2) then DMA moves RX FIFO of state machine 0 to TX FIFO state machine 1, 
# 3) then state machine 1 builds a 32-bit array one bit at a time.
# 4) then print the result bitstream from state machine 1 RX FIFO.

import time
from rp2 import PIO, asm_pio, StateMachine

@micropython.viper
def trigger_DMA(sm0):
    ptr32(0x50000430)[0] |= 0b00001  # triggers DMA chan0, reference 2.5.7 of the RP2040 Datasheet for DMA: MULTI_CHAN_TRIGGER Register

### State Machine 0
@rp2.asm_pio(in_shiftdir=0, out_shiftdir=1, autopull=True, pull_thresh=1, autopush=True, push_thresh=1)
def bounce():       # move a single bit from TX FIFO to RX FIFO
    wrap_target()

    out(x, 1)       # shift in one bit from OSR to scratch x
    in_(x, 1)       # shift out one bit from scratch x to ISR
    irq(rel(0))
    
    wrap()

def sm0_handler(sm0):
    print("sm0", sm0.get()) # used for debugging state machine 0

sm0 = rp2.StateMachine(0, bounce)
sm0.irq(trigger_DMA)    # Trigger DMA channel 0 to move data from sm0 RX FIFO to sm1 TX FIFO
sm0.active(1)

### State Machine 1
@rp2.asm_pio(in_shiftdir=0, out_shiftdir=1, autopull=True, pull_thresh=1, autopush=True, push_thresh=32) # set the bit order direction of OSR and ISR as well as autopull threshold to allow a single bit into the state machine while storing these bits in the ISR until full (32-bits) 
def build_bitstream():  # accumulate 32-bits to the RX FIFO one bit at a time from the TX FIFO
    wrap_target()

    set(y, 31)			# set scratch y to 31, this will count down for each bit to be added to ISR

    label("loop")
    pull(block)			# wait (block) for a 32-bit word to be added to the TX FIFO, then move the word to the OSR
    out(x, 1)			# move one bit from OSR to scratch x
    in_(x, 1)			# move one bit from scratch x to OSR
    jmp(y_dec, "loop")	# loop back unill 32 bits (bit stream) have filled the ISR
    
#    push(noblock)		# move the 32-bits from the ISR to the RX FIFO
    irq(rel(0))			# set IRQ flag which will trigger the IRQ handler to get the 32-bit word from the RX FIFO
    wrap()

def sm1_handler(sm1):
    SM1_RX_FIFO_Receive = sm1.get()
    print(bin(SM1_RX_FIFO_Receive))
    print("SM1_RX_FIFO_Receive")

sm1 = rp2.StateMachine(1, build_bitstream)	# build array of bit at clock speed
#sm1.irq(sm1_handler, trigger=1, hard=False) # uncomment to debug state machine 1
sm1.active(1)	# Start state machine

@micropython.viper
def configure_DMA():
    RXF0_addr = uint(0x50200020)    # address of RX FIFO register for State Machine 0
    TXF1_addr = uint(0x50200014)    # address of TX FIFO register for State Machine 1
    EN = 1              # Start channel upon setting the trigger register
    HIGH_PRIORITY = 1   # set DMA bus traffic priority as high
    DATA_SIZE = 2       # Transfer size: 0=byte, 1=half word, 2=word (default: 2)
    INCR_READ = 0       # No increment while reading
    INCR_WRITE = 0      # Non increment while writing
    RING_SIZE = 0       # No wrapping
    RING_SEL = 0        # No wrapping
    TREQ_SEL = 4        # select transfer rate of PIO0 RX FIFO, DREQ_PIO0_RX0
    CHAIN_TO = 0        # chain to DMA channel 1
    IRQ_QUIET = 1       # do not generate an interrupt
    BSWAP = 0           # do not reverse the order of the word
    SNIFF_EN = 0        # do not allow access to debug
    DMA_control_word = ((SNIFF_EN << 23) | (BSWAP << 22) | (IRQ_QUIET << 21) | (TREQ_SEL << 15) | 
                        (CHAIN_TO  << 11) | (RING_SEL << 10) |(RING_SIZE << 6) | (INCR_WRITE << 5) | 
                        (INCR_READ << 4) | (DATA_SIZE << 2) |(HIGH_PRIORITY << 1) | (EN << 0))
    # DMA channel 0 Alias 3, reference 2.5.2 of the RP2040 Datasheet regarding Aliases
    ptr32(0x5000003c)[0] = RXF0_addr            # DMA Channel 0 Read Address pointer <- RX FIFO register for State Machine 0, DMA0 read_adress alias register 3 (CH0_AL3_READ_ADDR_TRIG ) - trigger the DMA0 start
    ptr32(0x50000034)[0] = TXF1_addr            # DMA Channel 0 Write Address pointer -> TX FIFO register for State Machine 1 
    ptr32(0x50000038)[0] = 1                    # DMA Channel 0 Transfer Count <- Just one data (long) array to transfer continuously
    ptr32(0x50000030)[0] = DMA_control_word     # DMA Channel 0 Control and Status (using alias to not start immediately - will be started by DMA trigger register)


@micropython.viper
def enable_StateMachines():    
    ptr32(0x50200000)[0] |= 0b0011    # Enable PIO0 SM 0 and 1

@micropython.viper
def disable_StateMachines():
    ptr32(0x50000444)[0] |= 0b000011         # Aborts DMA chan0 and 1
    ptr32(0x50200000)[0] &= 0b111111110000   # Disable all PIO0 state machines

configure_DMA()
enable_StateMachines()

test_bitstream = 0b1111111111010100100101100010111000

# bit shift function
def get_bit(value, n):
    return ((value >> n & 1) != 0)

# write test_bitstream one bit at a time to state machine 0
for k in range(0, 4):
    for i in range(31,-1,-1):
        j = get_bit(test_bitstream, i)
        if j == 1:
            sm0.put(0b1)
        if j == 0:
            sm0.put(0b0)
        time.sleep_us(100)
        #print("write bit to sm0", i) # uncomment to debug
    #print("write loop", k) # uncomment to debug
    print(bin(sm1.get()))

print(bin(sm1.get()))
time.sleep(1)
disable_StateMachines()
machine.soft_reset()

0 replies

rkompass · 2024-10-05T15:29:55Z

rkompass
Oct 5, 2024

I was thinking of a solution for this without interrupts.
@sk8board don't feel bothered as you already have a working solution:-)
Still I want to share my thoughts/results:

Using my DMA class (which is somewhat outdated as it does not integrate the newer rp2.DMA functionality) I changed example 2 there to do a transfer of data from StateMachine 0 to StateMachine 4:

This is to be able to try out the functionality easily.
The settings of DMA parameters may be taken from the DMA class later, which itself is not too complicated (apart from the bootstrapping, which you may ignore).

# In this test we demonstrate the ability of DMA to transfer data between two PIO state machines.
#
#


from array import array
from time import sleep_ms, ticks_ms, ticks_diff
from rp2 import PIO, StateMachine, asm_pio

from rp2_dma import RP2_Dma

@asm_pio(push_thresh=32, in_shiftdir=PIO.SHIFT_LEFT, out_shiftdir=PIO.SHIFT_RIGHT)
def sm_gen():                       # generate numbers from 1 on upwards
    set(x, 0)
    label("incr")    # increment x by inverting, decrementing and inverting
    mov(x, invert(x))      [31]
    jmp(x_dec, "here")     [31]
    label("here")
    mov(x, invert(x))      [31]   # 32 x 25 = 800 instructions per loop
    mov(isr, x)            [31]   # could run with 2000 Hz: 
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    nop()                  [31]
    push(noblock)          [31]   #    0.4 s per push()  at 2000 Hz
    jmp("incr")            [31]

@asm_pio(push_thresh=32, in_shiftdir=PIO.SHIFT_LEFT, out_shiftdir=PIO.SHIFT_RIGHT)
def sm_copy():       # copy the numbers (lower 6 bits), from TX_FIFO to RX_FIFO
    pull(block)
    out(isr, 6)
    push(noblock)

smg = StateMachine(0, sm_gen, freq=2000)
smc = StateMachine(4, sm_copy, freq=2000)
dma = RP2_Dma(smg,  smc, count=1000, dreq=4) # dreq=8 for syncing with smc as destination, 4 for syncing with smg as source

dma.start()
smc.active(1)
smg.active(1)

ms_start = ticks_ms()                        # readout smc's FIFO if it contains something, for 20 seconds
while ticks_diff(ticks_ms(), ms_start) < 20_000:
    if smc.rx_fifo():
        print(smc.get())
    sleep_ms(100)

smg.active(0)
smc.active(0)

which works quite well.

It is essential to set the dreq parameter to the right value.
Here the DMA synchronization has to happen with the slower StateMachine.
Also deciding for the right option block/noblock in pushing and pulling to/from the FIFOs seems critical.
Here the faster StateMachine is the receiving one and it pulls blockingly.

You may try other settings.

@sk8board You mentioned the problem of re-triggering the DMA channel:

If your overall number of words is smaller than 2**32-1 then you may set the count parameter of the DMA to that value and be fine.
This is no option of course if you plan for a long-duration function or high data rates.

Alternatively, you might set up two such channels in identical manner and set them to re-trigger each other in ping-pong style.

Unfortunately a DMA channel cannot re-trigger itself, so there seems no other solution for this case that does not use a second channel or interrupts?!?

2 replies

sk8board Oct 5, 2024
Author

Thank you for your input.

I tried the ping-pong approach, but found the DMA would run at full speed and not sync with the speed of the state machine FIFO. Is there a way to sync with the state machine FIFO while using the ping-pong approach?

rkompass Oct 6, 2024

By using the right DREQ value the DMA can be made to be in lockstep with the slower StateMachine. The faster StateMachine will throttle down to DMA speed if it's transfers with DMA proceed blockingly.

My example code does exactly this.

Using the ping-pong has no effect on these relations, so it should be possible, preserving the relative synchronicity.

sk8board · 2024-10-07T02:30:15Z

sk8board
Oct 7, 2024
Author

I appreciate your help. I made a demo of DMA with two PIO state machines.

One DMA between two state machines. The other DMA from the second state machine to a data variable.

3 replies

rkompass Oct 7, 2024

I see, the dreq (there called treq) is there in your demo. I don't understand however, why the interrupts are still necessary.

Anyway, I changed my program slightly:

dma = RP2_Dma(smg, smc, count=1000, dreq=4) # dreq=8 for syncing with smc as destination, 4 for syncing with smg as source
is replaced by

dma1 = RP2_Dma(smg,  smc, count=1, dreq=4) # dreq=8 for syncing with smd as destination, 4 for syncing with smg as source
dma2 = RP2_Dma(smg,  smc, count=1, dreq=4)
dma1.chain_to(dma2)
dma2.chain_to(dma1)

and now the ping-pong of dma1 and dma2 makes an unlimited number of transfers possible.
I didn't try that before.

Iirc the RP2350 has an option to specify unlimited transfer count, so there you would only need one DMA channel.

Perhaps I should translate my example to the newer rp2.DMA style ...

sk8board Oct 8, 2024
Author

I see, the dreq (there called treq) is there in your demo.

Yes, according to the RP2040 datasheet, the name of the dreq bits are labeled treq_sel.

I don't understand however, why the interrupts are still necessary.

The reason for use of interrupts is that I cannot get ping-pong to work for my application. I am missing a key piece of information.

In my application (not my demo) the data rate of serial communication can vary from 100us to 1ms per bit. Should ping-pong DMA be able to support this variation in transfer rate?

the RP2350 has an option to specify unlimited transfer count, so there you would only need one DMA channel.

Good to know. The RP2350 also allows sharing data between state machines with two new mov instructions. This would eliminate one of my DMA channels. I have a Pico 2, but I am trying to persist with the RP2040 as I know my persistence will pay off with better understanding.

Perhaps I should translate my example to the newer rp2.DMA style ...

I cannot get your example to work. Therefore, I would be grateful if your example was updated.

Thank you for your help.

rkompass Oct 8, 2024

In my application (not my demo) the data rate of serial communication can vary from 100us to 1ms per bit. Should ping-pong DMA be able to support this variation in transfer rate?

Definitely. The ping-pong switch should not take longer than a single transfer, only a few nanoseconds.

I cannot get your example to work. Therefore, I would be grateful if your example was updated.

I will try to do that when I'm back home, unfortunately probably not very soon.

sk8board · 2024-10-09T17:55:41Z

sk8board
Oct 9, 2024
Author

I rewrote my DMA interrupt example with Viper and the use of pointers showed how to use DMA the chaining ping-pong method. I created a demo of it here.

0 replies

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Using DMA between Two State Machines, RP2040 Pico #15958

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