v0.3.0

Added

• Hardware support for:
  • Vector single-width integer multiply instructions (vmul, vmulh, vmulhu, vmulhsu)
  • Vector single-width integer multiply-add instructions (vmacc, vnmsac, vmadd, vnmsub)
  • Vector integer add-with-carry/subtract-with-borrow instructions (vadc, vsbc)
  • Vector widening integer multiply instructions (vwmul, vwmulu, vwmulsu)
  • Vector widening integer multiply-add instructions (vwmaccu, vwmacc, vwmaccsu, vwmaccus)

Changed

• Explicit scan chain signals added to the lane's and Ara's interfaces

Fixed

• Miscellaneous fixes for compatibility with Synopsys DC

v0.2.0

Added

• Hardware support for:
  • Bit-shift instructions (vsll, vsrl, vsra)
  • Vector widening integer add/subtract (vwadd, vwaddu, vwsub, vwsubu)
  • Vector integer extension (vzext, vsext)
  • Vector integer merge and move instructions (vmerge, vmv)
  • Vector narrowing integer right shift instructions (vnsrl, vnsra)

Changed

• Bender updated to version 0.21.0

Fixed

• CVA6's forwarding mechanism of operand B for accelerator instructions

v0.1.0

Added

• Hardware support for vector configuration instructions: vsetvl, vsetvli.
• Hardware support for basic arithmetic and logic instructions: vadd, vsub, vrsub, vmin(u), vmax(u), vand, vor, vxor.
• Hardware support for vector mask operations: vmand, vmnand, vmandnot, vmor, vmnor, vmornot, vmxor, vmxnor.
• Hardware support for masked instructions.
• Hardware support for vector length multipliers.
• Software support for vector code running on Ara.