Hierarchical verilator model

[huettern]

The verilator testbench is faster for cycle-accurate software benchmarks than VCS/VSIM simulators. Occamy is not yet fully verilator compatible. Verilating this many cores will require a lot of RAM and will likely not work.

This was the motivation to enable hierachical mode inside the Snitch cluster. Current effort can be seen in the verilator-hierachical branch.

Problems

• hierachical designs don't support parameter type parameters. This was mitigated by adding a wrapper around snitch_cc and passing the structs by their bit with and re-generating the structs before instantiating snitch_cc

Current progress

The model compiles but the first instructions to the FPU subsystem are not retired

fcvt.d.w ft0, zero             #; ac1  = 0
fcvt.d.w ft1, zero             #; ac1  = 0

The VSIM testbench works with the modifications enabled (adding ``define VERILATORand runmake bin/snitch_cluster.vsim`). Instructions offloaded to outside `snitch_cc` work too (`div/mul`). The `fcvt` instruction is offloaded to the FPU-SS that resides inside `snitch_cc` which due to the hierarchical mode cannot be inspected in the generated VCD.

This issue should serve as an entry-point for someone interested in picking this up again.

[huettern]

cc @SamuelRiedel