diff --git a/CHANGELOG.md b/CHANGELOG.md
index 1c9a8e1c..483c7be6 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -5,24 +5,33 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
 ## [Unreleased]
+
+## [4.0.1] - 2022-04-15
+### Fixed
+- Fix debug module addresses
+
 ## [4.0.0] - 2022-04-08
 ### Changed
 - Update RI5CY to CV32E40P
 - Remove PULP_TRAINING references
 ### Fixed
 - Wire up uart char and error events
+
 ## [3.3.0] - 2022-04-04
 ## Changed
 - Update riscv-dbg to v0.5.0 (synchronous jtag reset and bus error signaling)
+
 ## [3.2.0] - 2022-04-01
 ## Changed
 - Update bender dependency link for udma components, ibex, cv32e40p
 - Update interface for udma_i2c with unconnected `nack`
 ## Fixed
 - Fix ibex register file for FPGA
+
 ## [3.1.1] - 2022-03-11
 ### Fixed
 - Fix cdc reset signal for cluster
+
 ## [3.1.0] - 2022-03-09
 ### Changed
 - Added simulation stdout (replacing the hierarchical access in the tb hack)