From bdd8c8c9f7114c79e83e0a2cccf082d2110d6cd4 Mon Sep 17 00:00:00 2001
From: bluew <bluewww@users.noreply.github.com>
Date: Fri, 15 Apr 2022 17:31:36 +0200
Subject: [PATCH 1/2] Fix debug module addresses

* Derive from periph_bus_defines
* dm_exception_addr_i was set incorrectly (1a11_080c instead of 1a11_0808)
---
 rtl/fc/fc_subsystem.sv | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/rtl/fc/fc_subsystem.sv b/rtl/fc/fc_subsystem.sv
index 96e5f800..f8729a6e 100644
--- a/rtl/fc/fc_subsystem.sv
+++ b/rtl/fc/fc_subsystem.sv
@@ -8,6 +8,8 @@
 // CONDITIONS OF ANY KIND, either express or implied. See the License for the
 // specific language governing permissions and limitations under the License.
 
+`include "periph_bus_defines.sv"
+
 module fc_subsystem import cv32e40p_apu_core_pkg::*; #(
     parameter CORE_TYPE           = 0,
     parameter USE_XPULP           = 1,
@@ -169,9 +171,9 @@ module fc_subsystem import cv32e40p_apu_core_pkg::*; #(
         .scan_cg_en_i         (test_en_i),
         .boot_addr_i          (boot_addr),
         .mtvec_addr_i         (32'h0),
-        .dm_halt_addr_i       (32'h1A110800),
+        .dm_halt_addr_i       (`DEBUG_START_ADDR + dm::HaltAddress[31:0]),
         .hart_id_i            (hart_id),
-        .dm_exception_addr_i  (32'h1A11080C),
+        .dm_exception_addr_i  (`DEBUG_START_ADDR + dm::ExceptionAddress[31:0]),
 
         // Instruction memory interface
         .instr_req_o           (obi_instr_req),

From 86b59c29dcee900b8d5e4cc9615a80c4d1343586 Mon Sep 17 00:00:00 2001
From: bluew <bluewww@users.noreply.github.com>
Date: Fri, 15 Apr 2022 17:33:20 +0200
Subject: [PATCH 2/2] Update CHANGELOG.md

---
 CHANGELOG.md | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/CHANGELOG.md b/CHANGELOG.md
index 1c9a8e1c..483c7be6 100644
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -5,24 +5,33 @@ The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
 ## [Unreleased]
+
+## [4.0.1] - 2022-04-15
+### Fixed
+- Fix debug module addresses
+
 ## [4.0.0] - 2022-04-08
 ### Changed
 - Update RI5CY to CV32E40P
 - Remove PULP_TRAINING references
 ### Fixed
 - Wire up uart char and error events
+
 ## [3.3.0] - 2022-04-04
 ## Changed
 - Update riscv-dbg to v0.5.0 (synchronous jtag reset and bus error signaling)
+
 ## [3.2.0] - 2022-04-01
 ## Changed
 - Update bender dependency link for udma components, ibex, cv32e40p
 - Update interface for udma_i2c with unconnected `nack`
 ## Fixed
 - Fix ibex register file for FPGA
+
 ## [3.1.1] - 2022-03-11
 ### Fixed
 - Fix cdc reset signal for cluster
+
 ## [3.1.0] - 2022-03-09
 ### Changed
 - Added simulation stdout (replacing the hierarchical access in the tb hack)