From cc1ece1697fbc81309abdfd9d8a31abff0fc4bc6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christoph=20M=C3=BCllner?= Date: Sat, 8 Apr 2023 05:58:36 +0200 Subject: [PATCH] Add support for Zvkb MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch introduces support for Zvkb: - vandn.[vv,vx] - vbrev8.v - vclmul.[vv,vx] - vclmulh.[vv,vx] - vrev8.v Support for RV32 and RV64 is added, but both versions are identical. Signed-off-by: Christoph Müllner --- .../rv32i_m/Zvk/src/vandn.vv-01.S | 207 ++++++++++++++++++ .../rv32i_m/Zvk/src/vandn.vx-01.S | 207 ++++++++++++++++++ .../rv32i_m/Zvk/src/vbrev8.v-01.S | 206 +++++++++++++++++ .../rv32i_m/Zvk/src/vclmul.vv-01.S | 140 ++++++++++++ .../rv32i_m/Zvk/src/vclmul.vx-01.S | 140 ++++++++++++ .../rv32i_m/Zvk/src/vclmulh.vv-01.S | 140 ++++++++++++ .../rv32i_m/Zvk/src/vclmulh.vx-01.S | 140 ++++++++++++ riscv-test-suite/rv32i_m/Zvk/src/vrev8.v-01.S | 206 +++++++++++++++++ riscv-test-suite/rv32i_m/Zvk/src/vrol.vv-01.S | 207 ++++++++++++++++++ riscv-test-suite/rv32i_m/Zvk/src/vrol.vx-01.S | 207 ++++++++++++++++++ riscv-test-suite/rv32i_m/Zvk/src/vror.vi-01.S | 207 ++++++++++++++++++ riscv-test-suite/rv32i_m/Zvk/src/vror.vv-01.S | 207 ++++++++++++++++++ riscv-test-suite/rv32i_m/Zvk/src/vror.vx-01.S | 207 ++++++++++++++++++ .../rv64i_m/Zvk/src/vsha2ch-e32.vv-01.S | 159 ++++++++++++++ .../rv64i_m/Zvk/src/vsha2ch-e64.vv-01.S | 159 ++++++++++++++ .../rv64i_m/Zvk/src/vsha2cl-e32.vv-01.S | 159 ++++++++++++++ .../rv64i_m/Zvk/src/vsha2cl-e64.vv-01.S | 159 ++++++++++++++ .../rv64i_m/Zvk/src/vsha2ms-e32.vv-01.S | 159 ++++++++++++++ .../rv64i_m/Zvk/src/vsha2ms-e64.vv-01.S | 159 ++++++++++++++ 19 files changed, 3375 insertions(+) create mode 100644 riscv-test-suite/rv32i_m/Zvk/src/vandn.vv-01.S create mode 100644 riscv-test-suite/rv32i_m/Zvk/src/vandn.vx-01.S create mode 100644 riscv-test-suite/rv32i_m/Zvk/src/vbrev8.v-01.S create mode 100644 riscv-test-suite/rv32i_m/Zvk/src/vclmul.vv-01.S create mode 100644 riscv-test-suite/rv32i_m/Zvk/src/vclmul.vx-01.S create mode 100644 riscv-test-suite/rv32i_m/Zvk/src/vclmulh.vv-01.S create mode 100644 riscv-test-suite/rv32i_m/Zvk/src/vclmulh.vx-01.S create mode 100644 riscv-test-suite/rv32i_m/Zvk/src/vrev8.v-01.S create mode 100644 riscv-test-suite/rv32i_m/Zvk/src/vrol.vv-01.S create mode 100644 riscv-test-suite/rv32i_m/Zvk/src/vrol.vx-01.S create mode 100644 riscv-test-suite/rv32i_m/Zvk/src/vror.vi-01.S create mode 100644 riscv-test-suite/rv32i_m/Zvk/src/vror.vv-01.S create mode 100644 riscv-test-suite/rv32i_m/Zvk/src/vror.vx-01.S create mode 100644 riscv-test-suite/rv64i_m/Zvk/src/vsha2ch-e32.vv-01.S create mode 100644 riscv-test-suite/rv64i_m/Zvk/src/vsha2ch-e64.vv-01.S create mode 100644 riscv-test-suite/rv64i_m/Zvk/src/vsha2cl-e32.vv-01.S create mode 100644 riscv-test-suite/rv64i_m/Zvk/src/vsha2cl-e64.vv-01.S create mode 100644 riscv-test-suite/rv64i_m/Zvk/src/vsha2ms-e32.vv-01.S create mode 100644 riscv-test-suite/rv64i_m/Zvk/src/vsha2ms-e64.vv-01.S diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vandn.vv-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vandn.vv-01.S new file mode 100644 index 000000000..c5d0351c1 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvk/src/vandn.vv-01.S @@ -0,0 +1,207 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vandn.vv instruction. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvkb,RV64IV_Zicsr_Zvkb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvkb);def TEST_CASE_1=True;",vandn.vv) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VANDN.VV has the following inputs and outputs: +// - input VS1: Op1 (to be inverted) +// - input VS2: Op2 +// - input VM: Mask encoding ( or v0.t) +// - output VD: Result + +#define VINST vandn.vv + +inst_1x8: +// This test will define v0, which will later be used as mask register +TEST_CASE_VVV(1, 8, VINST, v0, v0, 0*8, v1, 1*8) +//sig[1*8] + +inst_2x8: +TEST_CASE_VVV(2, 8, VINST, v1, v2, 0*8, v3, 1*8) +//sig[2*8] + +inst_3x8: +TEST_CASE_VVV(3, 8, VINST, v4, v3, 0*8, v5, 3*8) +//sig[3*8] + +inst_4x8: +TEST_CASE_VVV(4, 8, VINST, v5, v6, 0*8, v7, 5*8) +//sig[4*8] + +inst_8x8: +TEST_CASE_VVV_M(8, 8, VINST, v8, v7, 0*8, v9, 7*8) +//sig[5*8] + +inst_16x8: +TEST_CASE_VVV(16, 8, VINST, v9, v10, 0*8, v11, 9*8) +//sig[7*8] + +inst_31x8: +TEST_CASE_VVV(31, 8, VINST, v12, v11, 0*8, v13, 11*8) +//sig[11*8] + + +inst_1x16: +TEST_CASE_VVV_M(1, 16, VINST, v13, v14, 0*8, v15, 2*8) +//sig[12*8] + +inst_2x16: +TEST_CASE_VVV(2, 16, VINST, v16, v15, 0*8, v17, 4*8) +//sig[13*8] + +inst_4x16: +TEST_CASE_VVV(4, 16, VINST, v17, v18, 0*8, v19, 6*8) +//sig[14*8] + +inst_8x16: +TEST_CASE_VVV(8, 16, VINST, v20, v19, 0*8, v21, 8*8) +//sig[16*8] + +inst_16x16: +TEST_CASE_VVV_M(16, 16, VINST, v21, v22, 0*8, v23, 10*8) +//sig[20*8] + +inst_31x16: +TEST_CASE_VVV(31, 16, VINST, v24, v23, 0*8, v25, 12*8) +//sig[28*8] + + +inst_1x32: +TEST_CASE_VVV(1, 32, VINST, v25, v26, 0*8, v27, 3*8) +//sig[29*8] + +inst_2x32: +TEST_CASE_VVV(2, 32, VINST, v28, v27, 0*8, v29, 5*8) +//sig[30*8] + +inst_4x32: +TEST_CASE_VVV(4, 32, VINST, v29, v30, 0*8, v31, 9*8) +//sig[32*8] + +inst_8x32: +TEST_CASE_VVV_M(8, 32, VINST, v1, v31, 0*8, v7, 7*8) +//sig[36*8] + +inst_16x32: +TEST_CASE_VVV(16, 32, VINST, v31, v31, 0*8, v1, 1*8) +//sig[44*8] + + +inst_1x64: +TEST_CASE_VVV(1, 64, VINST, v1, v3, 0*8, v3, 0*8) +//sig[45*8] + +inst_2x64: +TEST_CASE_VVV(2, 64, VINST, v2, v4, 0*8, v5, 5*8) +//sig[47*8] + +inst_4x64: +TEST_CASE_VVV(4, 64, VINST, v3, v5, 0*8, v7, 7*8) +//sig[51*8] + +inst_8x64: +TEST_CASE_VVV(8, 64, VINST, v4, v6, 0*8, v9, 9*8) +//sig[59*8] + + +inst_0: +TEST_CASE_VVV_M(1, 64, VINST, v5, v7, 8*8, v11, 11*8) +//sig[60*8] + +inst_1: +TEST_CASE_VVV(1, 64, VINST, v6, v8, 9*8, v13, 13*8) +//sig[61*8] + +inst_2: +TEST_CASE_VVV(1, 64, VINST, v7, v9, 10*8, v15, 15*8) +//sig[62*8] + +inst_3: +TEST_CASE_VVV(1, 64, VINST, v8, v10, 11*8, v17, 17*8) +//sig[63*8] + +inst_4: +TEST_CASE_VVV_M(1, 64, VINST, v9, v20, 12*8, v19, 19*8) +//sig[64*8] + +inst_5: +TEST_CASE_VVV(1, 64, VINST, v10, v30, 13*8, v31, 4*8) +//sig[65*8] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..127*8] + .fill 128, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vandn.vx-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vandn.vx-01.S new file mode 100644 index 000000000..88998c03d --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvk/src/vandn.vx-01.S @@ -0,0 +1,207 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vandn.vx instruction. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvkb,RV64IV_Zicsr_Zvkb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvkb);def TEST_CASE_1=True;",vandn.vx) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VANDN.VX has the following inputs and outputs: +// - input VS1: Op1 (to be inverted) +// - input VS2: Op2 +// - input VM: Mask encoding ( or v0.t) +// - output VD: Result + +#define VINST vandn.vx + +inst_1x8: +// This test will define v0, which will later be used as mask register +TEST_CASE_VVR(1, 8, VINST, v0, v0, 0*8, x7, 1*8) +//sig[1*8] + +inst_2x8: +TEST_CASE_VVR(2, 8, VINST, v1, v2, 0*8, x7, 1*8) +//sig[2*8] + +inst_3x8: +TEST_CASE_VVR(3, 8, VINST, v4, v3, 0*8, x7, 3*8) +//sig[3*8] + +inst_4x8: +TEST_CASE_VVR(4, 8, VINST, v5, v6, 0*8, x7, 5*8) +//sig[4*8] + +inst_8x8: +TEST_CASE_VVR_M(8, 8, VINST, v8, v7, 0*8, x9, 7*8) +//sig[5*8] + +inst_16x8: +TEST_CASE_VVR(16, 8, VINST, v9, v10, 0*8, x11, 9*8) +//sig[7*8] + +inst_31x8: +TEST_CASE_VVR(31, 8, VINST, v12, v11, 0*8, x13, 11*8) +//sig[11*8] + + +inst_1x16: +TEST_CASE_VVR_M(1, 16, VINST, v13, v14, 0*8, x15, 2*8) +//sig[12*8] + +inst_2x16: +TEST_CASE_VVR(2, 16, VINST, v16, v15, 0*8, x17, 4*8) +//sig[13*8] + +inst_4x16: +TEST_CASE_VVR(4, 16, VINST, v17, v18, 0*8, x19, 6*8) +//sig[14*8] + +inst_8x16: +TEST_CASE_VVR(8, 16, VINST, v20, v19, 0*8, x21, 8*8) +//sig[16*8] + +inst_16x16: +TEST_CASE_VVR_M(16, 16, VINST, v21, v22, 0*8, x23, 10*8) +//sig[20*8] + +inst_31x16: +TEST_CASE_VVR(31, 16, VINST, v24, v23, 0*8, x25, 12*8) +//sig[28*8] + + +inst_1x32: +TEST_CASE_VVR(1, 32, VINST, v25, v26, 0*8, x27, 3*8) +//sig[29*8] + +inst_2x32: +TEST_CASE_VVR(2, 32, VINST, v28, v27, 0*8, x29, 5*8) +//sig[30*8] + +inst_4x32: +TEST_CASE_VVR(4, 32, VINST, v29, v30, 0*8, x31, 9*8) +//sig[32*8] + +inst_8x32: +TEST_CASE_VVR_M(8, 32, VINST, v1, v31, 0*8, x7, 7*8) +//sig[36*8] + +inst_16x32: +TEST_CASE_VVR(16, 32, VINST, v31, v31, 0*8, x1, 1*8) +//sig[44*8] + + +inst_1x64: +TEST_CASE_VVR(1, 64, VINST, v1, v3, 0*8, x3, 0*8) +//sig[45*8] + +inst_2x64: +TEST_CASE_VVR(2, 64, VINST, v2, v4, 0*8, x5, 5*8) +//sig[47*8] + +inst_4x64: +TEST_CASE_VVR(4, 64, VINST, v3, v5, 0*8, x7, 7*8) +//sig[51*8] + +inst_8x64: +TEST_CASE_VVR(8, 64, VINST, v4, v6, 0*8, x9, 9*8) +//sig[59*8] + + +inst_0: +TEST_CASE_VVR_M(1, 64, VINST, v5, v7, 8*8, x11, 11*8) +//sig[60*8] + +inst_1: +TEST_CASE_VVR(1, 64, VINST, v6, v8, 9*8, x13, 13*8) +//sig[61*8] + +inst_2: +TEST_CASE_VVR(1, 64, VINST, v7, v9, 10*8, x15, 15*8) +//sig[62*8] + +inst_3: +TEST_CASE_VVR(1, 64, VINST, v8, v10, 11*8, x17, 17*8) +//sig[63*8] + +inst_4: +TEST_CASE_VVR_M(1, 64, VINST, v9, v20, 12*8, x19, 19*8) +//sig[64*8] + +inst_5: +TEST_CASE_VVR(1, 64, VINST, v10, v30, 13*8, x31, 4*8) +//sig[65*8] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..127*8] + .fill 128, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vbrev8.v-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vbrev8.v-01.S new file mode 100644 index 000000000..aa960aea6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvk/src/vbrev8.v-01.S @@ -0,0 +1,206 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vbrev8.v instruction. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvkb,RV64IV_Zicsr_Zvkb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvkb);def TEST_CASE_1=True;",vbrev8.v) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VBREV8.V has the following inputs and outputs: +// - input VS2: Input data +// - input VM: Mask encoding ( or v0.t) +// - output VD: Byte reversed data + +#define VINST vbrev8.v + +inst_1x8: +// This test will define v0, which will later be used as mask register +TEST_CASE_VV(1, 8, VINST, v0, v0, 0*8) +//sig[1*8] + +inst_2x8: +TEST_CASE_VV(2, 8, VINST, v1, v2, 0*8) +//sig[2*8] + +inst_3x8: +TEST_CASE_VV(3, 8, VINST, v4, v3, 0*8) +//sig[3*8] + +inst_4x8: +TEST_CASE_VV(4, 8, VINST, v5, v6, 0*8) +//sig[4*8] + +inst_8x8: +TEST_CASE_VV_M(8, 8, VINST, v8, v7, 0*8) +//sig[5*8] + +inst_16x8: +TEST_CASE_VV(16, 8, VINST, v9, v10, 0*8) +//sig[7*8] + +inst_31x8: +TEST_CASE_VV(31, 8, VINST, v12, v11, 0*8) +//sig[11*8] + + +inst_1x16: +TEST_CASE_VV_M(1, 16, VINST, v13, v14, 0*8) +//sig[12*8] + +inst_2x16: +TEST_CASE_VV(2, 16, VINST, v16, v15, 0*8) +//sig[13*8] + +inst_4x16: +TEST_CASE_VV(4, 16, VINST, v17, v18, 0*8) +//sig[14*8] + +inst_8x16: +TEST_CASE_VV(8, 16, VINST, v20, v19, 0*8) +//sig[16*8] + +inst_16x16: +TEST_CASE_VV_M(16, 16, VINST, v21, v22, 0*8) +//sig[20*8] + +inst_31x16: +TEST_CASE_VV(31, 16, VINST, v24, v23, 0*8) +//sig[28*8] + + +inst_1x32: +TEST_CASE_VV(1, 32, VINST, v25, v26, 0*8) +//sig[29*8] + +inst_2x32: +TEST_CASE_VV(2, 32, VINST, v28, v27, 0*8) +//sig[30*8] + +inst_4x32: +TEST_CASE_VV(4, 32, VINST, v29, v30, 0*8) +//sig[32*8] + +inst_8x32: +TEST_CASE_VV_M(8, 32, VINST, v1, v31, 0*8) +//sig[36*8] + +inst_16x32: +TEST_CASE_VV(16, 32, VINST, v31, v31, 0*8) +//sig[44*8] + + +inst_1x64: +TEST_CASE_VV(1, 64, VINST, v1, v3, 0*8) +//sig[45*8] + +inst_2x64: +TEST_CASE_VV(2, 64, VINST, v2, v4, 0*8) +//sig[47*8] + +inst_4x64: +TEST_CASE_VV(4, 64, VINST, v3, v5, 0*8) +//sig[51*8] + +inst_8x64: +TEST_CASE_VV(8, 64, VINST, v4, v6, 0*8) +//sig[59*8] + + +inst_0: +TEST_CASE_VV_M(1, 64, VINST, v5, v7, 8*8) +//sig[60*8] + +inst_1: +TEST_CASE_VV(1, 64, VINST, v6, v8, 9*8) +//sig[61*8] + +inst_2: +TEST_CASE_VV(1, 64, VINST, v7, v9, 10*8) +//sig[62*8] + +inst_3: +TEST_CASE_VV(1, 64, VINST, v8, v10, 11*8) +//sig[63*8] + +inst_4: +TEST_CASE_VV_M(1, 64, VINST, v9, v20, 12*8) +//sig[64*8] + +inst_5: +TEST_CASE_VV(1, 64, VINST, v10, v30, 13*8) +//sig[65*8] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..127*8] + .fill 128, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vclmul.vv-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vclmul.vv-01.S new file mode 100644 index 000000000..974eeb52a --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvk/src/vclmul.vv-01.S @@ -0,0 +1,140 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vclmul.vv instruction. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvkb,RV64IV_Zicsr_Zvkb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvkb);def TEST_CASE_1=True;",vclmul.vv) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VCLMUL.VV has the following inputs and outputs: +// - input VS1: Multiplier +// - input VS2: Multiplicand +// - input VM: Mask encoding ( or v0.t) +// - output VD: Carry-less product (low-half) +// VCLMUL.VV requires that SEW=64 + +#define VINST vclmul.vv + +inst_0: +// This test will define v0, which will later be used as mask register +TEST_CASE_VVV(1, 64, VINST, v0, v1, 0*8, v2, 1*8) +//sig[8*1] + +inst_1: +TEST_CASE_VVV(1, 64, VINST, v5, v4, 2*8, v3, 3*8) +//sig[8*2] + +inst_2: +TEST_CASE_VVV(1, 64, VINST, v6, v7, 4*8, v8, 5*8) +//sig[8*3] + +inst_3: +TEST_CASE_VVV(1, 64, VINST, v9, v10, 7*8, v11, 6*8) +//sig[8*4] + +inst_4: +TEST_CASE_VVV_M(2, 64, VINST, v12, v13, 2*8, v14, 3*8) +//sig[8*6] + +inst_5: +TEST_CASE_VVV(2, 64, VINST, v15, v16, 2*8, v17, 3*8) +//sig[8*8] + +inst_6: +TEST_CASE_VVV_M(2, 64, VINST, v18, v19, 2*8, v20, 3*8) +//sig[8*10] + +inst_7: +TEST_CASE_VVV_M(2, 64, VINST, v21, v22, 2*8, v23, 3*8) +//sig[8*12] + +inst_8: +TEST_CASE_VVV(4, 64, VINST, v24, v25, 0*8, v26, 4*8) +//sig[8*16] + +inst_9: +TEST_CASE_VVV(4, 64, VINST, v27, v28, 4*8, v29, 0*8) +//sig[8*20] + +inst_10: +TEST_CASE_VVV(4, 64, VINST, v30, v31, 0*8, v2, 0*8) +//sig[8*24] + +inst_11: +TEST_CASE_VVV_M(4, 64, VINST, v1, v15, 4*8, v31, 4*8) +//sig[8*28] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..127*8] + .fill 128, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vclmul.vx-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vclmul.vx-01.S new file mode 100644 index 000000000..84fdb981d --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvk/src/vclmul.vx-01.S @@ -0,0 +1,140 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vclmul.vx instruction. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvkb,RV64IV_Zicsr_Zvkb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvkb);def TEST_CASE_1=True;",vclmul.vx) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VCLMUL.VX has the following inputs and outputs: +// - input VS1: Multiplier +// - input VS2: Multiplicand +// - input VM: Mask encoding ( or v0.t) +// - output VD: Carry-less product (low-half) +// VCLMUL.VX requires that SEW=64 + +#define VINST vclmul.vx + +inst_0: +// This test will define v0, which will later be used as mask register +TEST_CASE_VVR(1, 64, VINST, v0, v1, 0*8, x7, 1*8) +//sig[8*1] + +inst_1: +TEST_CASE_VVR(1, 64, VINST, v5, v4, 2*8, x7, 3*8) +//sig[8*2] + +inst_2: +TEST_CASE_VVR(1, 64, VINST, v6, v7, 4*8, x8, 5*8) +//sig[8*3] + +inst_3: +TEST_CASE_VVR(1, 64, VINST, v9, v10, 7*8, x11, 6*8) +//sig[8*4] + +inst_4: +TEST_CASE_VVR_M(2, 64, VINST, v12, v13, 2*8, x14, 3*8) +//sig[8*6] + +inst_5: +TEST_CASE_VVR(2, 64, VINST, v15, v16, 2*8, x17, 3*8) +//sig[8*8] + +inst_6: +TEST_CASE_VVR_M(2, 64, VINST, v18, v19, 2*8, x20, 3*8) +//sig[8*10] + +inst_7: +TEST_CASE_VVR_M(2, 64, VINST, v21, v22, 2*8, x23, 3*8) +//sig[8*12] + +inst_8: +TEST_CASE_VVR(4, 64, VINST, v24, v25, 0*8, x26, 4*8) +//sig[8*16] + +inst_9: +TEST_CASE_VVR(4, 64, VINST, v27, v28, 4*8, x29, 0*8) +//sig[8*20] + +inst_10: +TEST_CASE_VVR(4, 64, VINST, v30, v31, 0*8, x7, 0*8) +//sig[8*24] + +inst_11: +TEST_CASE_VVR_M(4, 64, VINST, v1, v15, 4*8, x31, 4*8) +//sig[8*28] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..127*8] + .fill 128, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vclmulh.vv-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vclmulh.vv-01.S new file mode 100644 index 000000000..4ea020ee6 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvk/src/vclmulh.vv-01.S @@ -0,0 +1,140 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vclmulh.vv instruction. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvkb,RV64IV_Zicsr_Zvkb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvkb);def TEST_CASE_1=True;",vclmulh.vv) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VCLMULH.VV has the following inputs and outputs: +// - input VS1: Multiplier +// - input VS2: Multiplicand +// - input VM: Mask encoding ( or v0.t) +// - output VD: Carry-less product (low-half) +// VCLMULH.VV requires that SEW=64 + +#define VINST vclmulh.vv + +inst_0: +// This test will define v0, which will later be used as mask register +TEST_CASE_VVV(1, 64, VINST, v0, v1, 0*8, v2, 1*8) +//sig[8*1] + +inst_1: +TEST_CASE_VVV(1, 64, VINST, v5, v4, 2*8, v3, 3*8) +//sig[8*2] + +inst_2: +TEST_CASE_VVV(1, 64, VINST, v6, v7, 4*8, v8, 5*8) +//sig[8*3] + +inst_3: +TEST_CASE_VVV(1, 64, VINST, v9, v10, 7*8, v11, 6*8) +//sig[8*4] + +inst_4: +TEST_CASE_VVV_M(2, 64, VINST, v12, v13, 2*8, v14, 3*8) +//sig[8*6] + +inst_5: +TEST_CASE_VVV(2, 64, VINST, v15, v16, 2*8, v17, 3*8) +//sig[8*8] + +inst_6: +TEST_CASE_VVV_M(2, 64, VINST, v18, v19, 2*8, v20, 3*8) +//sig[8*10] + +inst_7: +TEST_CASE_VVV_M(2, 64, VINST, v21, v22, 2*8, v23, 3*8) +//sig[8*12] + +inst_8: +TEST_CASE_VVV(4, 64, VINST, v24, v25, 0*8, v26, 4*8) +//sig[8*16] + +inst_9: +TEST_CASE_VVV(4, 64, VINST, v27, v28, 4*8, v29, 0*8) +//sig[8*20] + +inst_10: +TEST_CASE_VVV(4, 64, VINST, v30, v31, 0*8, v2, 0*8) +//sig[8*24] + +inst_11: +TEST_CASE_VVV_M(4, 64, VINST, v1, v15, 4*8, v31, 4*8) +//sig[8*28] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..127*8] + .fill 128, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vclmulh.vx-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vclmulh.vx-01.S new file mode 100644 index 000000000..284b16d49 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvk/src/vclmulh.vx-01.S @@ -0,0 +1,140 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vclmulh.vx instruction. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvkb,RV64IV_Zicsr_Zvkb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvkb);def TEST_CASE_1=True;",vclmulh.vx) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VCLMULH.VX has the following inputs and outputs: +// - input VS1: Multiplier +// - input VS2: Multiplicand +// - input VM: Mask encoding ( or v0.t) +// - output VD: Carry-less product (low-half) +// VCLMULH.VX requires that SEW=64 + +#define VINST vclmulh.vx + +inst_0: +// This test will define v0, which will later be used as mask register +TEST_CASE_VVR(1, 64, VINST, v0, v1, 0*8, x7, 1*8) +//sig[8*1] + +inst_1: +TEST_CASE_VVR(1, 64, VINST, v5, v4, 2*8, x7, 3*8) +//sig[8*2] + +inst_2: +TEST_CASE_VVR(1, 64, VINST, v6, v7, 4*8, x8, 5*8) +//sig[8*3] + +inst_3: +TEST_CASE_VVR(1, 64, VINST, v9, v10, 7*8, x11, 6*8) +//sig[8*4] + +inst_4: +TEST_CASE_VVR_M(2, 64, VINST, v12, v13, 2*8, x14, 3*8) +//sig[8*6] + +inst_5: +TEST_CASE_VVR(2, 64, VINST, v15, v16, 2*8, x17, 3*8) +//sig[8*8] + +inst_6: +TEST_CASE_VVR_M(2, 64, VINST, v18, v19, 2*8, x20, 3*8) +//sig[8*10] + +inst_7: +TEST_CASE_VVR_M(2, 64, VINST, v21, v22, 2*8, x23, 3*8) +//sig[8*12] + +inst_8: +TEST_CASE_VVR(4, 64, VINST, v24, v25, 0*8, x26, 4*8) +//sig[8*16] + +inst_9: +TEST_CASE_VVR(4, 64, VINST, v27, v28, 4*8, x29, 0*8) +//sig[8*20] + +inst_10: +TEST_CASE_VVR(4, 64, VINST, v30, v31, 0*8, x7, 0*8) +//sig[8*24] + +inst_11: +TEST_CASE_VVR_M(4, 64, VINST, v1, v15, 4*8, x31, 4*8) +//sig[8*28] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..127*8] + .fill 128, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vrev8.v-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vrev8.v-01.S new file mode 100644 index 000000000..0dcfa9270 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvk/src/vrev8.v-01.S @@ -0,0 +1,206 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vrev8.v instruction. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvkb,RV64IV_Zicsr_Zvkb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvkb);def TEST_CASE_1=True;",vrev8.v) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VREV8.V has the following inputs and outputs: +// - input VS2: Input data +// - input VM: Mask encoding ( or v0.t) +// - output VD: Byte reversed data + +#define VINST vrev8.v + +inst_1x8: +// This test will define v0, which will later be used as mask register +TEST_CASE_VV(1, 8, VINST, v0, v0, 0*8) +//sig[1*8] + +inst_2x8: +TEST_CASE_VV(2, 8, VINST, v1, v2, 0*8) +//sig[2*8] + +inst_3x8: +TEST_CASE_VV(3, 8, VINST, v4, v3, 0*8) +//sig[3*8] + +inst_4x8: +TEST_CASE_VV(4, 8, VINST, v5, v6, 0*8) +//sig[4*8] + +inst_8x8: +TEST_CASE_VV_M(8, 8, VINST, v8, v7, 0*8) +//sig[5*8] + +inst_16x8: +TEST_CASE_VV(16, 8, VINST, v9, v10, 0*8) +//sig[7*8] + +inst_31x8: +TEST_CASE_VV(31, 8, VINST, v12, v11, 0*8) +//sig[11*8] + + +inst_1x16: +TEST_CASE_VV_M(1, 16, VINST, v13, v14, 0*8) +//sig[12*8] + +inst_2x16: +TEST_CASE_VV(2, 16, VINST, v16, v15, 0*8) +//sig[13*8] + +inst_4x16: +TEST_CASE_VV(4, 16, VINST, v17, v18, 0*8) +//sig[14*8] + +inst_8x16: +TEST_CASE_VV(8, 16, VINST, v20, v19, 0*8) +//sig[16*8] + +inst_16x16: +TEST_CASE_VV_M(16, 16, VINST, v21, v22, 0*8) +//sig[20*8] + +inst_31x16: +TEST_CASE_VV(31, 16, VINST, v24, v23, 0*8) +//sig[28*8] + + +inst_1x32: +TEST_CASE_VV(1, 32, VINST, v25, v26, 0*8) +//sig[29*8] + +inst_2x32: +TEST_CASE_VV(2, 32, VINST, v28, v27, 0*8) +//sig[30*8] + +inst_4x32: +TEST_CASE_VV(4, 32, VINST, v29, v30, 0*8) +//sig[32*8] + +inst_8x32: +TEST_CASE_VV_M(8, 32, VINST, v1, v31, 0*8) +//sig[36*8] + +inst_16x32: +TEST_CASE_VV(16, 32, VINST, v31, v31, 0*8) +//sig[44*8] + + +inst_1x64: +TEST_CASE_VV(1, 64, VINST, v1, v3, 0*8) +//sig[45*8] + +inst_2x64: +TEST_CASE_VV(2, 64, VINST, v2, v4, 0*8) +//sig[47*8] + +inst_4x64: +TEST_CASE_VV(4, 64, VINST, v3, v5, 0*8) +//sig[51*8] + +inst_8x64: +TEST_CASE_VV(8, 64, VINST, v4, v6, 0*8) +//sig[59*8] + + +inst_0: +TEST_CASE_VV_M(1, 64, VINST, v5, v7, 8*8) +//sig[60*8] + +inst_1: +TEST_CASE_VV(1, 64, VINST, v6, v8, 9*8) +//sig[61*8] + +inst_2: +TEST_CASE_VV(1, 64, VINST, v7, v9, 10*8) +//sig[62*8] + +inst_3: +TEST_CASE_VV(1, 64, VINST, v8, v10, 11*8) +//sig[63*8] + +inst_4: +TEST_CASE_VV_M(1, 64, VINST, v9, v20, 12*8) +//sig[64*8] + +inst_5: +TEST_CASE_VV(1, 64, VINST, v10, v30, 13*8) +//sig[65*8] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..127*8] + .fill 128, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vrol.vv-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vrol.vv-01.S new file mode 100644 index 000000000..3c3d575a2 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvk/src/vrol.vv-01.S @@ -0,0 +1,207 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vrol.vv instruction. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvkb,RV64IV_Zicsr_Zvkb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvkb);def TEST_CASE_1=True;",vrol.vv) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VROL.VV has the following inputs and outputs: +// - input VS1: Rotate amount +// - input VS2: Data +// - input VM: Mask encoding ( or v0.t) +// - output VD: Rotated data + +#define VINST vrol.vv + +inst_1x8: +// This test will define v0, which will later be used as mask register +TEST_CASE_VVV(1, 8, VINST, v0, v0, 0*8, v1, 1*8) +//sig[1*8] + +inst_2x8: +TEST_CASE_VVV(2, 8, VINST, v1, v2, 0*8, v3, 1*8) +//sig[2*8] + +inst_3x8: +TEST_CASE_VVV(3, 8, VINST, v4, v3, 0*8, v5, 3*8) +//sig[3*8] + +inst_4x8: +TEST_CASE_VVV(4, 8, VINST, v5, v6, 0*8, v7, 5*8) +//sig[4*8] + +inst_8x8: +TEST_CASE_VVV_M(8, 8, VINST, v8, v7, 0*8, v9, 7*8) +//sig[5*8] + +inst_16x8: +TEST_CASE_VVV(16, 8, VINST, v9, v10, 0*8, v11, 9*8) +//sig[7*8] + +inst_31x8: +TEST_CASE_VVV(31, 8, VINST, v12, v11, 0*8, v13, 11*8) +//sig[11*8] + + +inst_1x16: +TEST_CASE_VVV_M(1, 16, VINST, v13, v14, 0*8, v15, 2*8) +//sig[12*8] + +inst_2x16: +TEST_CASE_VVV(2, 16, VINST, v16, v15, 0*8, v17, 4*8) +//sig[13*8] + +inst_4x16: +TEST_CASE_VVV(4, 16, VINST, v17, v18, 0*8, v19, 6*8) +//sig[14*8] + +inst_8x16: +TEST_CASE_VVV(8, 16, VINST, v20, v19, 0*8, v21, 8*8) +//sig[16*8] + +inst_16x16: +TEST_CASE_VVV_M(16, 16, VINST, v21, v22, 0*8, v23, 10*8) +//sig[20*8] + +inst_31x16: +TEST_CASE_VVV(31, 16, VINST, v24, v23, 0*8, v25, 12*8) +//sig[28*8] + + +inst_1x32: +TEST_CASE_VVV(1, 32, VINST, v25, v26, 0*8, v27, 3*8) +//sig[29*8] + +inst_2x32: +TEST_CASE_VVV(2, 32, VINST, v28, v27, 0*8, v29, 5*8) +//sig[30*8] + +inst_4x32: +TEST_CASE_VVV(4, 32, VINST, v29, v30, 0*8, v31, 9*8) +//sig[32*8] + +inst_8x32: +TEST_CASE_VVV_M(8, 32, VINST, v1, v31, 0*8, v7, 7*8) +//sig[36*8] + +inst_16x32: +TEST_CASE_VVV(16, 32, VINST, v31, v31, 0*8, v1, 1*8) +//sig[44*8] + + +inst_1x64: +TEST_CASE_VVV(1, 64, VINST, v1, v3, 0*8, v3, 0*8) +//sig[45*8] + +inst_2x64: +TEST_CASE_VVV(2, 64, VINST, v2, v4, 0*8, v5, 5*8) +//sig[47*8] + +inst_4x64: +TEST_CASE_VVV(4, 64, VINST, v3, v5, 0*8, v7, 7*8) +//sig[51*8] + +inst_8x64: +TEST_CASE_VVV(8, 64, VINST, v4, v6, 0*8, v9, 9*8) +//sig[59*8] + + +inst_0: +TEST_CASE_VVV_M(1, 64, VINST, v5, v7, 8*8, v11, 11*8) +//sig[60*8] + +inst_1: +TEST_CASE_VVV(1, 64, VINST, v6, v8, 9*8, v13, 13*8) +//sig[61*8] + +inst_2: +TEST_CASE_VVV(1, 64, VINST, v7, v9, 10*8, v15, 15*8) +//sig[62*8] + +inst_3: +TEST_CASE_VVV(1, 64, VINST, v8, v10, 11*8, v17, 17*8) +//sig[63*8] + +inst_4: +TEST_CASE_VVV_M(1, 64, VINST, v9, v20, 12*8, v19, 19*8) +//sig[64*8] + +inst_5: +TEST_CASE_VVV(1, 64, VINST, v10, v30, 13*8, v31, 4*8) +//sig[65*8] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..127*8] + .fill 128, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vrol.vx-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vrol.vx-01.S new file mode 100644 index 000000000..bc8bd0851 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvk/src/vrol.vx-01.S @@ -0,0 +1,207 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vrol.vx instruction. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvkb,RV64IV_Zicsr_Zvkb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvkb);def TEST_CASE_1=True;",vrol.vx) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VROL.VX has the following inputs and outputs: +// - input VS1: Rotate amount +// - input VS2: Data +// - input VM: Mask encoding ( or v0.t) +// - output VD: Rotated data + +#define VINST vrol.vx + +inst_1x8: +// This test will define v0, which will later be used as mask register +TEST_CASE_VVR(1, 8, VINST, v0, v0, 0*8, x7, 1*8) +//sig[1*8] + +inst_2x8: +TEST_CASE_VVR(2, 8, VINST, v1, v2, 0*8, x7, 1*8) +//sig[2*8] + +inst_3x8: +TEST_CASE_VVR(3, 8, VINST, v4, v3, 0*8, x7, 3*8) +//sig[3*8] + +inst_4x8: +TEST_CASE_VVR(4, 8, VINST, v5, v6, 0*8, x7, 5*8) +//sig[4*8] + +inst_8x8: +TEST_CASE_VVR_M(8, 8, VINST, v8, v7, 0*8, x9, 7*8) +//sig[5*8] + +inst_16x8: +TEST_CASE_VVR(16, 8, VINST, v9, v10, 0*8, x11, 9*8) +//sig[7*8] + +inst_31x8: +TEST_CASE_VVR(31, 8, VINST, v12, v11, 0*8, x13, 11*8) +//sig[11*8] + + +inst_1x16: +TEST_CASE_VVR_M(1, 16, VINST, v13, v14, 0*8, x15, 2*8) +//sig[12*8] + +inst_2x16: +TEST_CASE_VVR(2, 16, VINST, v16, v15, 0*8, x17, 4*8) +//sig[13*8] + +inst_4x16: +TEST_CASE_VVR(4, 16, VINST, v17, v18, 0*8, x19, 6*8) +//sig[14*8] + +inst_8x16: +TEST_CASE_VVR(8, 16, VINST, v20, v19, 0*8, x21, 8*8) +//sig[16*8] + +inst_16x16: +TEST_CASE_VVR_M(16, 16, VINST, v21, v22, 0*8, x23, 10*8) +//sig[20*8] + +inst_31x16: +TEST_CASE_VVR(31, 16, VINST, v24, v23, 0*8, x25, 12*8) +//sig[28*8] + + +inst_1x32: +TEST_CASE_VVR(1, 32, VINST, v25, v26, 0*8, x27, 3*8) +//sig[29*8] + +inst_2x32: +TEST_CASE_VVR(2, 32, VINST, v28, v27, 0*8, x29, 5*8) +//sig[30*8] + +inst_4x32: +TEST_CASE_VVR(4, 32, VINST, v29, v30, 0*8, x31, 9*8) +//sig[32*8] + +inst_8x32: +TEST_CASE_VVR_M(8, 32, VINST, v1, v31, 0*8, x7, 7*8) +//sig[36*8] + +inst_16x32: +TEST_CASE_VVR(16, 32, VINST, v31, v31, 0*8, x1, 1*8) +//sig[44*8] + + +inst_1x64: +TEST_CASE_VVR(1, 64, VINST, v1, v3, 0*8, x3, 0*8) +//sig[45*8] + +inst_2x64: +TEST_CASE_VVR(2, 64, VINST, v2, v4, 0*8, x5, 5*8) +//sig[47*8] + +inst_4x64: +TEST_CASE_VVR(4, 64, VINST, v3, v5, 0*8, x7, 7*8) +//sig[51*8] + +inst_8x64: +TEST_CASE_VVR(8, 64, VINST, v4, v6, 0*8, x9, 9*8) +//sig[59*8] + + +inst_0: +TEST_CASE_VVR_M(1, 64, VINST, v5, v7, 8*8, x11, 11*8) +//sig[60*8] + +inst_1: +TEST_CASE_VVR(1, 64, VINST, v6, v8, 9*8, x13, 13*8) +//sig[61*8] + +inst_2: +TEST_CASE_VVR(1, 64, VINST, v7, v9, 10*8, x15, 15*8) +//sig[62*8] + +inst_3: +TEST_CASE_VVR(1, 64, VINST, v8, v10, 11*8, x17, 17*8) +//sig[63*8] + +inst_4: +TEST_CASE_VVR_M(1, 64, VINST, v9, v20, 12*8, x19, 19*8) +//sig[64*8] + +inst_5: +TEST_CASE_VVR(1, 64, VINST, v10, v30, 13*8, x31, 4*8) +//sig[65*8] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..127*8] + .fill 128, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vror.vi-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vror.vi-01.S new file mode 100644 index 000000000..6aba01de4 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvk/src/vror.vi-01.S @@ -0,0 +1,207 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vror.vi instruction. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvkb,RV64IV_Zicsr_Zvkb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvkb);def TEST_CASE_1=True;",vror.vi) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VROR.VI has the following inputs and outputs: +// - input UIMM: Rotate amount +// - input VS2: Data +// - input VM: Mask encoding ( or v0.t) +// - output VD: Rotated data + +#define VINST vror.vi + +inst_1x8: +// This test will define v0, which will later be used as mask register +TEST_CASE_VVU(1, 8, VINST, v0, v0, 0*8, 5) +//sig[1*8] + +inst_2x8: +TEST_CASE_VVU(2, 8, VINST, v1, v2, 0*8, 7) +//sig[2*8] + +inst_3x8: +TEST_CASE_VVU(3, 8, VINST, v4, v3, 0*8, 9) +//sig[3*8] + +inst_4x8: +TEST_CASE_VVU(4, 8, VINST, v5, v6, 0*8, 11) +//sig[4*8] + +inst_8x8: +TEST_CASE_VVU_M(8, 8, VINST, v8, v7, 0*8, 13) +//sig[5*8] + +inst_16x8: +TEST_CASE_VVU(16, 8, VINST, v9, v10, 0*8, 15) +//sig[7*8] + +inst_31x8: +TEST_CASE_VVU(31, 8, VINST, v12, v11, 0*8, 17) +//sig[11*8] + + +inst_1x16: +TEST_CASE_VVU_M(1, 16, VINST, v13, v14, 0*8, 19) +//sig[12*8] + +inst_2x16: +TEST_CASE_VVU(2, 16, VINST, v16, v15, 0*8, 21) +//sig[13*8] + +inst_4x16: +TEST_CASE_VVU(4, 16, VINST, v17, v18, 0*8, 23) +//sig[14*8] + +inst_8x16: +TEST_CASE_VVU(8, 16, VINST, v20, v19, 0*8, 25) +//sig[16*8] + +inst_16x16: +TEST_CASE_VVU_M(16, 16, VINST, v21, v22, 0*8, 27) +//sig[20*8] + +inst_31x16: +TEST_CASE_VVU(31, 16, VINST, v24, v23, 0*8, 29) +//sig[28*8] + + +inst_1x32: +TEST_CASE_VVU(1, 32, VINST, v25, v26, 0*8, 31) +//sig[29*8] + +inst_2x32: +TEST_CASE_VVU(2, 32, VINST, v28, v27, 0*8, 0) +//sig[30*8] + +inst_4x32: +TEST_CASE_VVU(4, 32, VINST, v29, v30, 0*8, 2) +//sig[32*8] + +inst_8x32: +TEST_CASE_VVU_M(8, 32, VINST, v1, v31, 0*8, 4) +//sig[36*8] + +inst_16x32: +TEST_CASE_VVU(16, 32, VINST, v31, v31, 0*8, 6) +//sig[44*8] + + +inst_1x64: +TEST_CASE_VVU(1, 64, VINST, v1, v3, 0*8, 8) +//sig[45*8] + +inst_2x64: +TEST_CASE_VVU(2, 64, VINST, v2, v4, 0*8, 10) +//sig[47*8] + +inst_4x64: +TEST_CASE_VVU(4, 64, VINST, v3, v5, 0*8, 12) +//sig[51*8] + +inst_8x64: +TEST_CASE_VVU(8, 64, VINST, v4, v6, 0*8, 14) +//sig[59*8] + + +inst_0: +TEST_CASE_VVU_M(1, 64, VINST, v5, v7, 8*8, 16) +//sig[60*8] + +inst_1: +TEST_CASE_VVU(1, 64, VINST, v6, v8, 9*8, 18) +//sig[61*8] + +inst_2: +TEST_CASE_VVU(1, 64, VINST, v7, v9, 10*8, 20) +//sig[62*8] + +inst_3: +TEST_CASE_VVU(1, 64, VINST, v8, v10, 11*8, 22) +//sig[63*8] + +inst_4: +TEST_CASE_VVU_M(1, 64, VINST, v9, v20, 12*8, 24) +//sig[64*8] + +inst_5: +TEST_CASE_VVU(1, 64, VINST, v10, v30, 13*8, 30) +//sig[65*8] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..127*8] + .fill 128, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vror.vv-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vror.vv-01.S new file mode 100644 index 000000000..a04aa90ac --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvk/src/vror.vv-01.S @@ -0,0 +1,207 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vror.vv instruction. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvkb,RV64IV_Zicsr_Zvkb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvkb);def TEST_CASE_1=True;",vror.vv) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VROR.VV has the following inputs and outputs: +// - input VS1: Rotate amount +// - input VS2: Data +// - input VM: Mask encoding ( or v0.t) +// - output VD: Rotated data + +#define VINST vror.vv + +inst_1x8: +// This test will define v0, which will later be used as mask register +TEST_CASE_VVV(1, 8, VINST, v0, v0, 0*8, v1, 1*8) +//sig[1*8] + +inst_2x8: +TEST_CASE_VVV(2, 8, VINST, v1, v2, 0*8, v3, 1*8) +//sig[2*8] + +inst_3x8: +TEST_CASE_VVV(3, 8, VINST, v4, v3, 0*8, v5, 3*8) +//sig[3*8] + +inst_4x8: +TEST_CASE_VVV(4, 8, VINST, v5, v6, 0*8, v7, 5*8) +//sig[4*8] + +inst_8x8: +TEST_CASE_VVV_M(8, 8, VINST, v8, v7, 0*8, v9, 7*8) +//sig[5*8] + +inst_16x8: +TEST_CASE_VVV(16, 8, VINST, v9, v10, 0*8, v11, 9*8) +//sig[7*8] + +inst_31x8: +TEST_CASE_VVV(31, 8, VINST, v12, v11, 0*8, v13, 11*8) +//sig[11*8] + + +inst_1x16: +TEST_CASE_VVV_M(1, 16, VINST, v13, v14, 0*8, v15, 2*8) +//sig[12*8] + +inst_2x16: +TEST_CASE_VVV(2, 16, VINST, v16, v15, 0*8, v17, 4*8) +//sig[13*8] + +inst_4x16: +TEST_CASE_VVV(4, 16, VINST, v17, v18, 0*8, v19, 6*8) +//sig[14*8] + +inst_8x16: +TEST_CASE_VVV(8, 16, VINST, v20, v19, 0*8, v21, 8*8) +//sig[16*8] + +inst_16x16: +TEST_CASE_VVV_M(16, 16, VINST, v21, v22, 0*8, v23, 10*8) +//sig[20*8] + +inst_31x16: +TEST_CASE_VVV(31, 16, VINST, v24, v23, 0*8, v25, 12*8) +//sig[28*8] + + +inst_1x32: +TEST_CASE_VVV(1, 32, VINST, v25, v26, 0*8, v27, 3*8) +//sig[29*8] + +inst_2x32: +TEST_CASE_VVV(2, 32, VINST, v28, v27, 0*8, v29, 5*8) +//sig[30*8] + +inst_4x32: +TEST_CASE_VVV(4, 32, VINST, v29, v30, 0*8, v31, 9*8) +//sig[32*8] + +inst_8x32: +TEST_CASE_VVV_M(8, 32, VINST, v1, v31, 0*8, v7, 7*8) +//sig[36*8] + +inst_16x32: +TEST_CASE_VVV(16, 32, VINST, v31, v31, 0*8, v1, 1*8) +//sig[44*8] + + +inst_1x64: +TEST_CASE_VVV(1, 64, VINST, v1, v3, 0*8, v3, 0*8) +//sig[45*8] + +inst_2x64: +TEST_CASE_VVV(2, 64, VINST, v2, v4, 0*8, v5, 5*8) +//sig[47*8] + +inst_4x64: +TEST_CASE_VVV(4, 64, VINST, v3, v5, 0*8, v7, 7*8) +//sig[51*8] + +inst_8x64: +TEST_CASE_VVV(8, 64, VINST, v4, v6, 0*8, v9, 9*8) +//sig[59*8] + + +inst_0: +TEST_CASE_VVV_M(1, 64, VINST, v5, v7, 8*8, v11, 11*8) +//sig[60*8] + +inst_1: +TEST_CASE_VVV(1, 64, VINST, v6, v8, 9*8, v13, 13*8) +//sig[61*8] + +inst_2: +TEST_CASE_VVV(1, 64, VINST, v7, v9, 10*8, v15, 15*8) +//sig[62*8] + +inst_3: +TEST_CASE_VVV(1, 64, VINST, v8, v10, 11*8, v17, 17*8) +//sig[63*8] + +inst_4: +TEST_CASE_VVV_M(1, 64, VINST, v9, v20, 12*8, v19, 19*8) +//sig[64*8] + +inst_5: +TEST_CASE_VVV(1, 64, VINST, v10, v30, 13*8, v31, 4*8) +//sig[65*8] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..127*8] + .fill 128, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv32i_m/Zvk/src/vror.vx-01.S b/riscv-test-suite/rv32i_m/Zvk/src/vror.vx-01.S new file mode 100644 index 000000000..d84a21fa5 --- /dev/null +++ b/riscv-test-suite/rv32i_m/Zvk/src/vror.vx-01.S @@ -0,0 +1,207 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vror.vx instruction. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvkb,RV64IV_Zicsr_Zvkb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvkb);def TEST_CASE_1=True;",vror.vx) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VROR.VX has the following inputs and outputs: +// - input VS1: Rotate amount +// - input VS2: Data +// - input VM: Mask encoding ( or v0.t) +// - output VD: Rotated data + +#define VINST vror.vx + +inst_1x8: +// This test will define v0, which will later be used as mask register +TEST_CASE_VVR(1, 8, VINST, v0, v0, 0*8, x7, 1*8) +//sig[1*8] + +inst_2x8: +TEST_CASE_VVR(2, 8, VINST, v1, v2, 0*8, x7, 1*8) +//sig[2*8] + +inst_3x8: +TEST_CASE_VVR(3, 8, VINST, v4, v3, 0*8, x7, 3*8) +//sig[3*8] + +inst_4x8: +TEST_CASE_VVR(4, 8, VINST, v5, v6, 0*8, x7, 5*8) +//sig[4*8] + +inst_8x8: +TEST_CASE_VVR_M(8, 8, VINST, v8, v7, 0*8, x9, 7*8) +//sig[5*8] + +inst_16x8: +TEST_CASE_VVR(16, 8, VINST, v9, v10, 0*8, x11, 9*8) +//sig[7*8] + +inst_31x8: +TEST_CASE_VVR(31, 8, VINST, v12, v11, 0*8, x13, 11*8) +//sig[11*8] + + +inst_1x16: +TEST_CASE_VVR_M(1, 16, VINST, v13, v14, 0*8, x15, 2*8) +//sig[12*8] + +inst_2x16: +TEST_CASE_VVR(2, 16, VINST, v16, v15, 0*8, x17, 4*8) +//sig[13*8] + +inst_4x16: +TEST_CASE_VVR(4, 16, VINST, v17, v18, 0*8, x19, 6*8) +//sig[14*8] + +inst_8x16: +TEST_CASE_VVR(8, 16, VINST, v20, v19, 0*8, x21, 8*8) +//sig[16*8] + +inst_16x16: +TEST_CASE_VVR_M(16, 16, VINST, v21, v22, 0*8, x23, 10*8) +//sig[20*8] + +inst_31x16: +TEST_CASE_VVR(31, 16, VINST, v24, v23, 0*8, x25, 12*8) +//sig[28*8] + + +inst_1x32: +TEST_CASE_VVR(1, 32, VINST, v25, v26, 0*8, x27, 3*8) +//sig[29*8] + +inst_2x32: +TEST_CASE_VVR(2, 32, VINST, v28, v27, 0*8, x29, 5*8) +//sig[30*8] + +inst_4x32: +TEST_CASE_VVR(4, 32, VINST, v29, v30, 0*8, x31, 9*8) +//sig[32*8] + +inst_8x32: +TEST_CASE_VVR_M(8, 32, VINST, v1, v31, 0*8, x7, 7*8) +//sig[36*8] + +inst_16x32: +TEST_CASE_VVR(16, 32, VINST, v31, v31, 0*8, x1, 1*8) +//sig[44*8] + + +inst_1x64: +TEST_CASE_VVR(1, 64, VINST, v1, v3, 0*8, x3, 0*8) +//sig[45*8] + +inst_2x64: +TEST_CASE_VVR(2, 64, VINST, v2, v4, 0*8, x5, 5*8) +//sig[47*8] + +inst_4x64: +TEST_CASE_VVR(4, 64, VINST, v3, v5, 0*8, x7, 7*8) +//sig[51*8] + +inst_8x64: +TEST_CASE_VVR(8, 64, VINST, v4, v6, 0*8, x9, 9*8) +//sig[59*8] + + +inst_0: +TEST_CASE_VVR_M(1, 64, VINST, v5, v7, 8*8, x11, 11*8) +//sig[60*8] + +inst_1: +TEST_CASE_VVR(1, 64, VINST, v6, v8, 9*8, x13, 13*8) +//sig[61*8] + +inst_2: +TEST_CASE_VVR(1, 64, VINST, v7, v9, 10*8, x15, 15*8) +//sig[62*8] + +inst_3: +TEST_CASE_VVR(1, 64, VINST, v8, v10, 11*8, x17, 17*8) +//sig[63*8] + +inst_4: +TEST_CASE_VVR_M(1, 64, VINST, v9, v20, 12*8, x19, 19*8) +//sig[64*8] + +inst_5: +TEST_CASE_VVR(1, 64, VINST, v10, v30, 13*8, x31, 4*8) +//sig[65*8] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..127*8] + .fill 128, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zvk/src/vsha2ch-e32.vv-01.S b/riscv-test-suite/rv64i_m/Zvk/src/vsha2ch-e32.vv-01.S new file mode 100644 index 000000000..65d6b5436 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zvk/src/vsha2ch-e32.vv-01.S @@ -0,0 +1,159 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vsha2ch.vv instruction for SEW=32. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvknha,RV64IV_Zicsr_Zvknha") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvknha);def TEST_CASE_1=True;",vsha2ch.vv) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VSHA2CH.VV has the following inputs and outputs: +// - input VD: Current state {c, d, g, h} +// - input VS1: MessageSched plus constant[3:0] +// - input VS2: Current state {a, b, e, f} +// - output VD: Next state {a, b, e, f} +// VSHA2CH.VV requires that SEW=32 (or 64) and AVL=multiple of 4 + +#define VINST vsha2ch.vv + +inst_0: +TEST_CASE_WVV(4, 32, VINST, v0, 0*4, v1, 0*4, v2, 0*4) +//sig[4*4] + +inst_1: +TEST_CASE_WVV(8, 32, VINST, v3, 1*4, v2, 0*4, v30, 20*4) +//sig[12*4] + +inst_2: +TEST_CASE_WVV(12, 32, VINST, v4, 2*4, v5, 2*4, v28, 18*4) +//sig[24*4] + +inst_3: +TEST_CASE_WVV(16, 32, VINST, v7, 0*4, v6, 0*4, v26, 16*4) +//sig[40*4] + +inst_4: +TEST_CASE_WVV(20, 32, VINST, v8, 2*4, v9, 3*4, v24, 14*4) +//sig[60*4] + +inst_5: +TEST_CASE_WVV(24, 32, VINST, v11, 2*4, v10, 3*4, v22, 12*4) +//sig[84*4] + +inst_6: +TEST_CASE_WVV(28, 32, VINST, v12, 2*4, v13, 3*4, v20, 10*4) +//sig[112*4] + +inst_7: +TEST_CASE_WVV(4, 32, VINST, v15, 2*4, v14, 3*4, v18, 8*4) +//sig[116*4] + +inst_8: +TEST_CASE_WVV(4, 32, VINST, v16, 0*4, v17, 4*4, v16, 0*4) +//sig[120*4] + +inst_9: +TEST_CASE_WVV(4, 32, VINST, v19, 4*4, v18, 0*4, v14, 4*4) +//sig[124*4] + +inst_10: +TEST_CASE_WVV(4, 32, VINST, v20, 0*4, v21, 0*4, v12, 2*4) +//sig[128*4] + +inst_11: +TEST_CASE_WVV(4, 32, VINST, v20, 0*4, v21, 11*4, v10, 0*4) +//sig[132*4] + +inst_12: +TEST_CASE_WVV(4, 32, VINST, v23, 2*4, v22, 9*4, v8, 8*4) +//sig[136*4] + +inst_13: +TEST_CASE_WVV(4, 32, VINST, v24, 4*4, v25, 7*4, v6, 6*4) +//sig[140*4] + +inst_14: +TEST_CASE_WVV(4, 32, VINST, v27, 6*4, v26, 5*4, v4, 4*4) +//sig[144*4] + +inst_15: +TEST_CASE_WVV(4, 32, VINST, v28, 8*4, v29, 3*4, v2, 2*4) +//sig[148*4] + +inst_16: +TEST_CASE_WVV(4, 32, VINST, v31, 10*4, v30, 1*4, v0, 0*4) +//sig[156*4] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*4..255*4] + .fill 256, 4, 0xdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zvk/src/vsha2ch-e64.vv-01.S b/riscv-test-suite/rv64i_m/Zvk/src/vsha2ch-e64.vv-01.S new file mode 100644 index 000000000..b8471918a --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zvk/src/vsha2ch-e64.vv-01.S @@ -0,0 +1,159 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vsha2ch.vv instruction for SEW=64. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvknhb,RV64IV_Zicsr_Zvknhb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvknhb);def TEST_CASE_1=True;",vsha2ch.vv) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VSHA2CH.VV has the following inputs and outputs: +// - input VD: Current state {c, d, g, h} +// - input VS1: MessageSched plus constant[3:0] +// - input VS2: Current state {a, b, e, f} +// - output VD: Next state {a, b, e, f} +// VSHA2CH.VV requires that SEW=64 (or 32) and AVL=multiple of 4 + +#define VINST vsha2ch.vv + +inst_0: +TEST_CASE_WVV(4, 64, VINST, v0, 0*8, v1, 0*8, v2, 0*8) +//sig[4*8] + +inst_1: +TEST_CASE_WVV(8, 64, VINST, v3, 1*8, v2, 0*8, v30, 20*8) +//sig[12*8] + +inst_2: +TEST_CASE_WVV(12, 64, VINST, v4, 2*8, v5, 2*8, v28, 18*8) +//sig[24*8] + +inst_3: +TEST_CASE_WVV(16, 64, VINST, v7, 0*8, v6, 0*8, v26, 16*8) +//sig[40*8] + +inst_4: +TEST_CASE_WVV(20, 64, VINST, v8, 2*8, v9, 3*8, v24, 14*8) +//sig[60*8] + +inst_5: +TEST_CASE_WVV(24, 64, VINST, v11, 2*8, v10, 3*8, v22, 12*8) +//sig[84*8] + +inst_6: +TEST_CASE_WVV(28, 64, VINST, v12, 2*8, v13, 3*8, v20, 10*8) +//sig[112*8] + +inst_7: +TEST_CASE_WVV(4, 64, VINST, v15, 2*8, v14, 3*8, v18, 8*8) +//sig[116*8] + +inst_8: +TEST_CASE_WVV(4, 64, VINST, v16, 0*8, v17, 4*8, v16, 0*8) +//sig[120*8] + +inst_9: +TEST_CASE_WVV(4, 64, VINST, v19, 4*8, v18, 0*8, v14, 4*8) +//sig[124*8] + +inst_10: +TEST_CASE_WVV(4, 64, VINST, v20, 0*8, v21, 0*8, v12, 2*8) +//sig[128*8] + +inst_11: +TEST_CASE_WVV(4, 64, VINST, v20, 0*8, v21, 11*8, v10, 0*8) +//sig[132*8] + +inst_12: +TEST_CASE_WVV(4, 64, VINST, v23, 2*8, v22, 9*8, v8, 8*8) +//sig[136*8] + +inst_13: +TEST_CASE_WVV(4, 64, VINST, v24, 4*8, v25, 7*8, v6, 6*8) +//sig[140*8] + +inst_14: +TEST_CASE_WVV(4, 64, VINST, v27, 6*8, v26, 5*8, v4, 4*8) +//sig[144*8] + +inst_15: +TEST_CASE_WVV(4, 64, VINST, v28, 8*8, v29, 3*8, v2, 2*8) +//sig[148*8] + +inst_16: +TEST_CASE_WVV(4, 64, VINST, v31, 10*8, v30, 1*8, v0, 0*8) +//sig[156*8] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..255*8] + .fill 256, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zvk/src/vsha2cl-e32.vv-01.S b/riscv-test-suite/rv64i_m/Zvk/src/vsha2cl-e32.vv-01.S new file mode 100644 index 000000000..1ae270a55 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zvk/src/vsha2cl-e32.vv-01.S @@ -0,0 +1,159 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vsha2cl.vv instruction for SEW=32. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvknha,RV64IV_Zicsr_Zvknha") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvknha);def TEST_CASE_1=True;",vsha2cl.vv) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VSHA2CL.VV has the following inputs and outputs: +// - input VD: Current state {c, d, g, h} +// - input VS1: MessageSched plus constant[3:0] +// - input VS2: Current state {a, b, e, f} +// - output VD: Next state {a, b, e, f} +// VSHA2CL.VV requires that SEW=32 (or 64) and AVL=multiple of 4 + +#define VINST vsha2cl.vv + +inst_0: +TEST_CASE_WVV(4, 32, VINST, v0, 0*4, v1, 0*4, v2, 0*4) +//sig[4*4] + +inst_1: +TEST_CASE_WVV(8, 32, VINST, v3, 1*4, v2, 0*4, v30, 20*4) +//sig[12*4] + +inst_2: +TEST_CASE_WVV(12, 32, VINST, v4, 2*4, v5, 2*4, v28, 18*4) +//sig[24*4] + +inst_3: +TEST_CASE_WVV(16, 32, VINST, v7, 0*4, v6, 0*4, v26, 16*4) +//sig[40*4] + +inst_4: +TEST_CASE_WVV(20, 32, VINST, v8, 2*4, v9, 3*4, v24, 14*4) +//sig[60*4] + +inst_5: +TEST_CASE_WVV(24, 32, VINST, v11, 2*4, v10, 3*4, v22, 12*4) +//sig[84*4] + +inst_6: +TEST_CASE_WVV(28, 32, VINST, v12, 2*4, v13, 3*4, v20, 10*4) +//sig[112*4] + +inst_7: +TEST_CASE_WVV(4, 32, VINST, v15, 2*4, v14, 3*4, v18, 8*4) +//sig[116*4] + +inst_8: +TEST_CASE_WVV(4, 32, VINST, v16, 0*4, v17, 4*4, v16, 0*4) +//sig[120*4] + +inst_9: +TEST_CASE_WVV(4, 32, VINST, v19, 4*4, v18, 0*4, v14, 4*4) +//sig[124*4] + +inst_10: +TEST_CASE_WVV(4, 32, VINST, v20, 0*4, v21, 0*4, v12, 2*4) +//sig[128*4] + +inst_11: +TEST_CASE_WVV(4, 32, VINST, v20, 0*4, v21, 11*4, v10, 0*4) +//sig[132*4] + +inst_12: +TEST_CASE_WVV(4, 32, VINST, v23, 2*4, v22, 9*4, v8, 8*4) +//sig[136*4] + +inst_13: +TEST_CASE_WVV(4, 32, VINST, v24, 4*4, v25, 7*4, v6, 6*4) +//sig[140*4] + +inst_14: +TEST_CASE_WVV(4, 32, VINST, v27, 6*4, v26, 5*4, v4, 4*4) +//sig[144*4] + +inst_15: +TEST_CASE_WVV(4, 32, VINST, v28, 8*4, v29, 3*4, v2, 2*4) +//sig[148*4] + +inst_16: +TEST_CASE_WVV(4, 32, VINST, v31, 10*4, v30, 1*4, v0, 0*4) +//sig[156*4] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*4..255*4] + .fill 256, 4, 0xdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zvk/src/vsha2cl-e64.vv-01.S b/riscv-test-suite/rv64i_m/Zvk/src/vsha2cl-e64.vv-01.S new file mode 100644 index 000000000..e7985d4b0 --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zvk/src/vsha2cl-e64.vv-01.S @@ -0,0 +1,159 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vsha2cl.vv instruction for SEW=64. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvknhb,RV64IV_Zicsr_Zvknhb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvknhb);def TEST_CASE_1=True;",vsha2cl.vv) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VSHA2CL.VV has the following inputs and outputs: +// - input VD: Current state {c, d, g, h} +// - input VS1: MessageSched plus constant[3:0] +// - input VS2: Current state {a, b, e, f} +// - output VD: Next state {a, b, e, f} +// VSHA2CL.VV requires that SEW=64 (or 32) and AVL=multiple of 4 + +#define VINST vsha2cl.vv + +inst_0: +TEST_CASE_WVV(4, 64, VINST, v0, 0*8, v1, 0*8, v2, 0*8) +//sig[4*8] + +inst_1: +TEST_CASE_WVV(8, 64, VINST, v3, 1*8, v2, 0*8, v30, 20*8) +//sig[12*8] + +inst_2: +TEST_CASE_WVV(12, 64, VINST, v4, 2*8, v5, 2*8, v28, 18*8) +//sig[24*8] + +inst_3: +TEST_CASE_WVV(16, 64, VINST, v7, 0*8, v6, 0*8, v26, 16*8) +//sig[40*8] + +inst_4: +TEST_CASE_WVV(20, 64, VINST, v8, 2*8, v9, 3*8, v24, 14*8) +//sig[60*8] + +inst_5: +TEST_CASE_WVV(24, 64, VINST, v11, 2*8, v10, 3*8, v22, 12*8) +//sig[84*8] + +inst_6: +TEST_CASE_WVV(28, 64, VINST, v12, 2*8, v13, 3*8, v20, 10*8) +//sig[112*8] + +inst_7: +TEST_CASE_WVV(4, 64, VINST, v15, 2*8, v14, 3*8, v18, 8*8) +//sig[116*8] + +inst_8: +TEST_CASE_WVV(4, 64, VINST, v16, 0*8, v17, 4*8, v16, 0*8) +//sig[120*8] + +inst_9: +TEST_CASE_WVV(4, 64, VINST, v19, 4*8, v18, 0*8, v14, 4*8) +//sig[124*8] + +inst_10: +TEST_CASE_WVV(4, 64, VINST, v20, 0*8, v21, 0*8, v12, 2*8) +//sig[128*8] + +inst_11: +TEST_CASE_WVV(4, 64, VINST, v20, 0*8, v21, 11*8, v10, 0*8) +//sig[132*8] + +inst_12: +TEST_CASE_WVV(4, 64, VINST, v23, 2*8, v22, 9*8, v8, 8*8) +//sig[136*8] + +inst_13: +TEST_CASE_WVV(4, 64, VINST, v24, 4*8, v25, 7*8, v6, 6*8) +//sig[140*8] + +inst_14: +TEST_CASE_WVV(4, 64, VINST, v27, 6*8, v26, 5*8, v4, 4*8) +//sig[144*8] + +inst_15: +TEST_CASE_WVV(4, 64, VINST, v28, 8*8, v29, 3*8, v2, 2*8) +//sig[148*8] + +inst_16: +TEST_CASE_WVV(4, 64, VINST, v31, 10*8, v30, 1*8, v0, 0*8) +//sig[156*8] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..255*8] + .fill 256, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zvk/src/vsha2ms-e32.vv-01.S b/riscv-test-suite/rv64i_m/Zvk/src/vsha2ms-e32.vv-01.S new file mode 100644 index 000000000..69eb7d71e --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zvk/src/vsha2ms-e32.vv-01.S @@ -0,0 +1,159 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vsha2ms.vv instruction for SEW=32. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvknha,RV64IV_Zicsr_Zvknha") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvknha);def TEST_CASE_1=True;",vsha2ms.vv) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VSHA2MS.VV has the following inputs and outputs: +// - input VD: Message words {W[3], W[2], W[1], W[0]} +// - input VS1: Message words {W[15], W[14], -, W[12]} +// - input VS2: Message words {W[11], W[10], W[9], W[4]} +// - output VD: Message words {W[19], W[18], W[17], W[16]} +// VSHA2MS.VV requires that SEW=32 (or 64) and AVL=multiple of 4 + +#define VINST vsha2ms.vv + +inst_0: +TEST_CASE_WVV(4, 32, VINST, v0, 0*4, v1, 0*4, v2, 0*4) +//sig[4*4] + +inst_1: +TEST_CASE_WVV(8, 32, VINST, v3, 1*4, v2, 0*4, v30, 20*4) +//sig[12*4] + +inst_2: +TEST_CASE_WVV(12, 32, VINST, v4, 2*4, v5, 2*4, v28, 18*4) +//sig[24*4] + +inst_3: +TEST_CASE_WVV(16, 32, VINST, v7, 0*4, v6, 0*4, v26, 16*4) +//sig[40*4] + +inst_4: +TEST_CASE_WVV(20, 32, VINST, v8, 2*4, v9, 3*4, v24, 14*4) +//sig[60*4] + +inst_5: +TEST_CASE_WVV(24, 32, VINST, v11, 2*4, v10, 3*4, v22, 12*4) +//sig[84*4] + +inst_6: +TEST_CASE_WVV(28, 32, VINST, v12, 2*4, v13, 3*4, v20, 10*4) +//sig[112*4] + +inst_7: +TEST_CASE_WVV(4, 32, VINST, v15, 2*4, v14, 3*4, v18, 8*4) +//sig[116*4] + +inst_8: +TEST_CASE_WVV(4, 32, VINST, v16, 0*4, v17, 4*4, v16, 0*4) +//sig[120*4] + +inst_9: +TEST_CASE_WVV(4, 32, VINST, v19, 4*4, v18, 0*4, v14, 4*4) +//sig[124*4] + +inst_10: +TEST_CASE_WVV(4, 32, VINST, v20, 0*4, v21, 0*4, v12, 2*4) +//sig[128*4] + +inst_11: +TEST_CASE_WVV(4, 32, VINST, v20, 0*4, v21, 11*4, v10, 0*4) +//sig[132*4] + +inst_12: +TEST_CASE_WVV(4, 32, VINST, v23, 2*4, v22, 9*4, v8, 8*4) +//sig[136*4] + +inst_13: +TEST_CASE_WVV(4, 32, VINST, v24, 4*4, v25, 7*4, v6, 6*4) +//sig[140*4] + +inst_14: +TEST_CASE_WVV(4, 32, VINST, v27, 6*4, v26, 5*4, v4, 4*4) +//sig[144*4] + +inst_15: +TEST_CASE_WVV(4, 32, VINST, v28, 8*4, v29, 3*4, v2, 2*4) +//sig[148*4] + +inst_16: +TEST_CASE_WVV(4, 32, VINST, v31, 10*4, v30, 1*4, v0, 0*4) +//sig[156*4] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*4..255*4] + .fill 256, 4, 0xdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END diff --git a/riscv-test-suite/rv64i_m/Zvk/src/vsha2ms-e64.vv-01.S b/riscv-test-suite/rv64i_m/Zvk/src/vsha2ms-e64.vv-01.S new file mode 100644 index 000000000..5d39d449e --- /dev/null +++ b/riscv-test-suite/rv64i_m/Zvk/src/vsha2ms-e64.vv-01.S @@ -0,0 +1,159 @@ +// Copyright (c) 2023. RISC-V International. All rights reserved. +// SPDX-License-Identifier: BSD-3-Clause +// ----------- +// This assembly file tests the vsha2ms.vv instruction for SEW=64. + +// Define special purpose registers before including test_macros_vector.h +#define DATA_BASE x3 +#define SIG_BASE x4 +#define VLENB_CACHE x5 +#define HELPER_GPR x6 + +#include "test_macros_vector.h" + +RVTEST_ISA("RV32IV_Zicsr_Zvknhb,RV64IV_Zicsr_Zvknhb") + +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: +RVMODEL_BOOT + +RVTEST_CODE_BEGIN + +#ifdef TEST_CASE_1 + +RVTEST_CASE(0,"//check ISA:=regex(.*I.*V.*Zicsr.*Zvknhb);def TEST_CASE_1=True;",vsha2ms.vv) + +RVTEST_V_ENABLE() +RVTEST_VALBASEUPD(DATA_BASE, dataset_tc1) +RVTEST_SIGBASE(SIG_BASE, signature_tc1) + +// VSHA2MS.VV has the following inputs and outputs: +// - input VD: Message words {W[3], W[2], W[1], W[0]} +// - input VS1: Message words {W[15], W[14], -, W[12]} +// - input VS2: Message words {W[11], W[10], W[9], W[4]} +// - output VD: Message words {W[19], W[18], W[17], W[16]} +// VSHA2MS.VV requires that SEW=64 (or 32) and AVL=multiple of 4 + +#define VINST vsha2ms.vv + +inst_0: +TEST_CASE_WVV(4, 64, VINST, v0, 0*8, v1, 0*8, v2, 0*8) +//sig[4*8] + +inst_1: +TEST_CASE_WVV(8, 64, VINST, v3, 1*8, v2, 0*8, v30, 20*8) +//sig[12*8] + +inst_2: +TEST_CASE_WVV(12, 64, VINST, v4, 2*8, v5, 2*8, v28, 18*8) +//sig[24*8] + +inst_3: +TEST_CASE_WVV(16, 64, VINST, v7, 0*8, v6, 0*8, v26, 16*8) +//sig[40*8] + +inst_4: +TEST_CASE_WVV(20, 64, VINST, v8, 2*8, v9, 3*8, v24, 14*8) +//sig[60*8] + +inst_5: +TEST_CASE_WVV(24, 64, VINST, v11, 2*8, v10, 3*8, v22, 12*8) +//sig[84*8] + +inst_6: +TEST_CASE_WVV(28, 64, VINST, v12, 2*8, v13, 3*8, v20, 10*8) +//sig[112*8] + +inst_7: +TEST_CASE_WVV(4, 64, VINST, v15, 2*8, v14, 3*8, v18, 8*8) +//sig[116*8] + +inst_8: +TEST_CASE_WVV(4, 64, VINST, v16, 0*8, v17, 4*8, v16, 0*8) +//sig[120*8] + +inst_9: +TEST_CASE_WVV(4, 64, VINST, v19, 4*8, v18, 0*8, v14, 4*8) +//sig[124*8] + +inst_10: +TEST_CASE_WVV(4, 64, VINST, v20, 0*8, v21, 0*8, v12, 2*8) +//sig[128*8] + +inst_11: +TEST_CASE_WVV(4, 64, VINST, v20, 0*8, v21, 11*8, v10, 0*8) +//sig[132*8] + +inst_12: +TEST_CASE_WVV(4, 64, VINST, v23, 2*8, v22, 9*8, v8, 8*8) +//sig[136*8] + +inst_13: +TEST_CASE_WVV(4, 64, VINST, v24, 4*8, v25, 7*8, v6, 6*8) +//sig[140*8] + +inst_14: +TEST_CASE_WVV(4, 64, VINST, v27, 6*8, v26, 5*8, v4, 4*8) +//sig[144*8] + +inst_15: +TEST_CASE_WVV(4, 64, VINST, v28, 8*8, v29, 3*8, v2, 2*8) +//sig[148*8] + +inst_16: +TEST_CASE_WVV(4, 64, VINST, v31, 10*8, v30, 1*8, v0, 0*8) +//sig[156*8] + +#endif // TEST_CASE_1 + +RVTEST_CODE_END + +RVMODEL_HALT + +RVTEST_DATA_BEGIN +.word 0xbabecafe // trapreg_sv +.word 0xabecafeb // tramptbl_sv +.word 0xbecafeba // mtvec_save +.word 0xecafebab // mscratch_save + + .p2align 6 +dataset_tc1: +TEST_CASE_BLOCK_256B_0 +RVTEST_DATA_END + +RVMODEL_DATA_BEGIN +rvtest_sig_begin: +sig_begin_canary: +CANARY; + +signature_tc1: + //sig[0*8..255*8] + .fill 256, 8, 0xdeadbeefdeadbeef + +#ifdef rvtest_mtrap_routine + +tsig_begin_canary: +CANARY; +tsig_begin_canary: +CANARY; +mtrap_sigptr: + .fill 64*(XLEN/32),4,0xdeadbeef +tsig_end_canary: +CANARY; +tsig_end_canary: +CANARY; + +#endif // rvtest_mtrap_routine + +#ifdef rvtest_gpr_save + +gpr_save: + .fill 32*XLEN/32,4,0xdeadbeef + +#endif // rvtest_gpr_save + +sig_end_canary: +CANARY; +rvtest_sig_end: +RVMODEL_DATA_END