From 6e44fd5b63c0ccac6064ba3029cc78505ddc9afc Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Wed, 21 Aug 2024 13:53:16 -0700 Subject: [PATCH] Clarify Memory Access acts like data access. I'm not sure if this is necessary. Does RISC-V allow data loads to differ from instruction fetches? For a long time any mention of caches was avoided in all specs. Inspired by #1062. --- xml/abstract_commands.xml | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/xml/abstract_commands.xml b/xml/abstract_commands.xml index 0833aea0..8b6168e4 100644 --- a/xml/abstract_commands.xml +++ b/xml/abstract_commands.xml @@ -179,10 +179,11 @@ same project unless stated otherwise. This command lets the debugger perform memory accesses, - with the exact same memory view and permissions as the selected - hart has. This includes access to hart-local memory-mapped - registers, etc. The command performs the following sequence of - operations: + with the exact same memory view and permissions as performing + loads/stores on the selected hart. + This includes access to hart-local memory-mapped + registers, etc. The command performs the following sequence of + operations: . Copy data from the memory location specified in `arg1` into the `arg0` portion of `data`, if {accessregister-write} is clear.