From e3671acb460c6d4d4dbece0369be0bfbb6f6a4aa Mon Sep 17 00:00:00 2001 From: Tim Newsome Date: Tue, 15 Aug 2023 14:02:56 -0700 Subject: [PATCH] Recommend debug ROM is not cached. The performance of this code doesn't matter (compared to how slow JTAG is), and the fewer side effects debugging has, the better. --- implementations.tex | 2 ++ 1 file changed, 2 insertions(+) diff --git a/implementations.tex b/implementations.tex index d7352fbb..e938e413 100644 --- a/implementations.tex +++ b/implementations.tex @@ -30,6 +30,8 @@ \section{Execution Based} \label{execution_based} to the selected harts. This interrupt causes each hart to enter Debug Mode and jump to a defined memory region that is serviced by the DM and is only accessible to the harts in Debug Mode. +Accesses to this memory should be uncached to avoid side effects from +debugging operations. When taking this jump, \Rpc is saved to \RcsrDpc and \FcsrDcsrCause is updated in \RcsrDcsr. This jump is similar to a trap but it is not architecturally considered a trap, so for instance doesn't count as a trap for trigger behavior.