Build does not meet timing

[xobs]

The design runs in a single clock domain, driven by clki. This pin is a 48 MHz signal, and as a result the entire design actually runs at 48 MHz.

As a result, the system is overclocked and can fail on some devices:

Info: Max frequency for clock 'clk_48mhz': 32.13 MHz (PASS at 12.00 MHz)

[arblake]

My suggestion is that when a host device, computer, connected to the fomu hardware, that computer initialises its com. port toggling the tx line causing the fomu hardware to go into an unknown state. Re-powering the device causes it to return to a state to a dfu accessible device.

[rob-ng15]

Have redesigned j1eforth for the FOMU and have it working back on the HACKER board. I have built for PVT, but am unable to test.

[ulixxe]

Maybe you can try my USB-CDC implementation, in which you can use a lower clock for j1eforth design.
Look at https://github.com/ulixxe/usb_cdc

[rob-ng15]

Thanks, I'll give that a try. Looks nice!

…

On Tue, 23 Nov 2021 at 16:22, ulixxe ***@***.***> wrote: Maybe you can try my USB-CDC implementation, in which you can use a lower clock for j1eforth design. Look at https://github.com/ulixxe/usb_cdc — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#8 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AN4SYT245XQTCFJ2FEV7PZ3UNO5SZANCNFSM4SNX7VNQ> .

[rob-ng15]

Hi there, Tried wiring it in as https://github.com/rob-ng15/Silice-Playground/tree/master/j1eforth/FOMU-TEST the connection to the USB_CDC is in frameworks/fomu_USB_SPRAM.v Whilst it builds, it does not create a working ttyACM0, probably a mis-understanding on my part as to how to wire it in. Rob.

…

On Thu, 25 Nov 2021 at 13:03, Rob Shelton ***@***.***> wrote: Thanks, I'll give that a try. Looks nice! On Tue, 23 Nov 2021 at 16:22, ulixxe ***@***.***> wrote: > Maybe you can try my USB-CDC implementation, in which you can use a lower > clock for j1eforth design. > Look at https://github.com/ulixxe/usb_cdc > > — > You are receiving this because you commented. > Reply to this email directly, view it on GitHub > <#8 (comment)>, > or unsubscribe > <https://github.com/notifications/unsubscribe-auth/AN4SYT245XQTCFJ2FEV7PZ3UNO5SZANCNFSM4SNX7VNQ> > . >

[ulixxe]

Hi Rob,
Yes, there are some wrong connections.

1. .rstn_i signal is active low. So, at the end of the reset phase, it must be high. Whereas the top reset signal is active high.
   You can change it with:

         .rstn_i     (~reset),

2. IO buffers are outside of USB_CDC. So you have to instantiate them at the top, like:

        // pins
        .tx_en_o            ( tx_en ),
        .tx_dp_o            ( tx_dp ),
        .tx_dn_o            ( tx_dn ),
        .rx_dp_i            ( rx_dp ),
        .rx_dn_i            ( rx_dn ),
...
   SB_IO #(.PIN_TYPE(6'b101001),                                                                                               
           .PULLUP(1'b0))                                                                                                      
   u_usb_p (.PACKAGE_PIN(usb_dp),                                                                                               
            .OUTPUT_ENABLE(tx_en),                                                                                             
            .D_OUT_0(tx_dp),                                                                                                   
            .D_IN_0(rx_dp),                                                                                                    
            .D_OUT_1(1'b0),                                                                                                    
            .D_IN_1(),                                                                                                         
            .CLOCK_ENABLE(1'b0),                                                                                               
            .LATCH_INPUT_VALUE(1'b0),                                                                                          
            .INPUT_CLK(1'b0),                                                                                                  
            .OUTPUT_CLK(1'b0));                                                                                                
                                                                                                                               
   SB_IO #(.PIN_TYPE(6'b101001),                                                                                               
           .PULLUP(1'b0))                                                                                                      
   u_usb_n (.PACKAGE_PIN(usb_dn),                                                                                               
            .OUTPUT_ENABLE(tx_en),                                                                                             
            .D_OUT_0(tx_dn),                                                                                                   
            .D_IN_0(rx_dn),                                                                                                    
            .D_OUT_1(1'b0),                                                                                                    
            .D_IN_1(),                                                                                                         
            .CLOCK_ENABLE(1'b0),                                                                                               
            .LATCH_INPUT_VALUE(1'b0),                                                                                          
            .INPUT_CLK(1'b0),                                                                                                  
            .OUTPUT_CLK(1'b0));                                                                                                

3. I see clk_usb=24MHz. It is better if it is 48MHz. You can leave clk=12MHz. So you have to change PLL settings accordingly (for example with DIVR = 0, DIVF = 63, DIVQ = 4) and to configure USB_CDC with:

  // usb uart - this instanciates the entire USB device.
  usb_cdc #(
             .VENDORID(16'h0483),
             .PRODUCTID(16'h5740),
             .USE_APP_CLK(1))
   uart (
             .clk_i      (clk_usb),
             .app_clk_i  (clk),
             .rstn_i (~reset),

I hope this helps.