`riscv`: atomic read-write of CSRs

[sbutz]

From AIA V1.0:

It is almost always a mistake to write to a *topei CSR without a simultaneous read to learn which interrupt was claimed. Note especially, if a read of a *topei register and a subsequent write to the register are done by two separate CSR instructions, then a higher-priority interrupt may become newly pending-and-enabled in the interrupt file between the two instructions, causing the write to clear the pending bit of the new interrupt and not the one reported by the read. Once the pending bit of the new interrupt is cleared, the interrupt is lost. If it is necessary first to read a *topei CSR and then subsequently claim the interrupt as a separate step, the claim can be safely done by clearing the pending bit in the eip array via *siselect and *sireg, instead of writing to *topei.

I propose we add methods to *topei to atomically read and clear the CSR.

Related to #226