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Updates for Plasticine #219

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6 of 9 tasks
dkoeplin opened this issue Aug 29, 2017 · 6 comments
Open
6 of 9 tasks

Updates for Plasticine #219

dkoeplin opened this issue Aug 29, 2017 · 6 comments
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@dkoeplin
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dkoeplin commented Aug 29, 2017

The following compiler changes should take effect when PIR gen is enabled:

  • 1. Change switches to always be controllers (includes unit pipe insertion for conditions) [Priority 1]
  • 2. Change unrolled loops w/ enables to unrolled switches [Priority 1]
  • 3. Banking analysis on which access belong to which bank statically whenever possible. Place holder metadata banksOf [Priority 2]
  • 4. Remove Parallel from IR [Priority 2]
  • 5. Change LUT to SRAM (add metadata for initial value of SRAM and LUT) [Priority 2]
  • 6. Disable buffer coalescing [Priority 2]
  • 7. Transform Switch w/o effects or children and with return value to muxes [Priority 2]
  • 8. Change RegFile (no shift register) to SRAM (add metadata for initial value of SRAM and LUT) [Priority 3] Hold off for this
  • 9. Add analysis to figure out which dimension of the sram is paralleled accessed across InnerController's inner most index. The resulting dimensions should be <= 1.
@dkoeplin dkoeplin self-assigned this Aug 29, 2017
@yaqiz01
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yaqiz01 commented Aug 29, 2017

I made some changes to the list with priority (smaller means more important). You can check off tasks when they are in develop. Thanks!

@dkoeplin
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dkoeplin commented Sep 1, 2017

2 - Need to discuss with Matt - may change FPGA correctness
3 - Will be added with overhaul to banked accesses
7 - Requires representation of one-hot mux for Plasticine (or some other agreed upon thing)

@mattfel1
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mattfel1 commented Sep 1, 2017

2 - Seems like it won't change correctness, but it sounds more expensive maybe. The plan is to get rid of the enables that come into controllers and instead wrap them inside switches?

@yaqiz01
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yaqiz01 commented Sep 1, 2017

Can 7 be converted to nested muxes? For example

If (c1) b1 else if (c2) b2 else b3
can be converted to
Mux (c1, b1, mux(c2, b2, b3))

We can add one hot mux but ALUs have max 3 operands. so won't be albe to support selection more than two inputs

@dkoeplin
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dkoeplin commented Sep 1, 2017

@mattfel1 yeah that's the general idea. Plasticine doesn't support enables on reads/writes/etc., so it always needs explicit enabling controllers around these things.

@yaqiz01 yeah you're right I think that should work.

@yaqiz01
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yaqiz01 commented Sep 25, 2017

@dkoeplin For 1 is it possible to set Switch around the Switch Cases to have OuterControl ControlLevel? The only thing that's InnerControl level are the inner most switch cases

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