axi-stream
Here are 28 public repositories matching this topic...
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.
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Nov 21, 2023 - TeX
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
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Dec 3, 2023 - C
Synchronous and Asynchronous FIFO with AXI interface
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Nov 20, 2019 - SystemVerilog
FPGA implementation for UART interface for rx/tx data with support AXI-Stream protocol
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Dec 2, 2021 - SystemVerilog
A 2x2 mesh NoC compatible with AXI streaming interface
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Aug 8, 2020 - Coq
Zynq PS connected to a Hermes networkn-on-chip router via AXI streaming interface
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Aug 8, 2020 - Tcl
Notes after working with Zynq platform using vivado and petalinux
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Feb 26, 2024 - SystemVerilog
An IP used for testing AXI stream protocols. It uses a LFSR to generate ready and valid signals
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Aug 10, 2020 - Tcl
A one-position buffer compatible with AXI Stream interface
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Jan 17, 2024 - VHDL
A test IP that receives a packet from the NoC, increments its the payload, and sends the packet back to the source
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Jul 25, 2020 - Tcl
Fast bwa-mem dna matching algor implemented in system verilog, fully synthesizable.
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Apr 9, 2022 - Stata
FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device
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Feb 20, 2023 - C
FPGA interface and driver for an OV7670 camera sensor.
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Aug 28, 2023 - VHDL
This project is designed to delay the output of the video stream in AXI-STREAM format.
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Jul 14, 2024 - Verilog
Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.
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Aug 3, 2023 - VHDL
A one-position buffer compatible with AXI Stream interface
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May 23, 2023 - Tcl
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