A small collection of tutorials and tools for ASIC design.
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Updated
May 16, 2017 - SystemVerilog
A small collection of tutorials and tools for ASIC design.
🌟 Jasmine "lnishan" Chen's Curriculum Vitae (CV) in Markdown
Typical project for Synopsys DC Compiler
Example of a full DC synthesis script for a simple design
[WIP] Dockerize Synopsys/Cadence EDA tools
Technology file parser in Rust
This is a tutorial on standard digital design flow
Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
Fully pipelined DLX Microprocessor optimized for energy efficiency and testing purposes developed in VHDL. Simulation with Intel® ModelSim®, synthesis under Synopsys® DC Ultra™, and physical layout using Cadence® Innovus™ Implementation System.
Optimisation procedure written in tcl for (Area, Delay, Power) with the usage of Dual-Vth CMOS technology within Synopsys DC and PT
Ansible Role: Polaris - Installs and configures Polaris CLI
Command completion for Synopsys (Black Duck) Detect commands
2 bit random number generation under data encryption using Synopsys Custom Compiler in 32nm CMOS Technology
Designing a Pseudo dynamic latched comparator in 28nm CMOS Technology using Synopsys Tools.
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