APB verification using UVM
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Updated
Aug 21, 2023 - SystemVerilog
APB verification using UVM
This repository contains information about Digital Logic Design (ecen 3233) laboratory elements for Fall 2023.
100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
A simple SystemVerilog simulation tool written in rust
Two incoherent Caches interacting with single memory through memory_access_arbiter. Cache reads address 0x53 from memory upon cache_miss. After that it writes to that address but that cache entry becomes dirty/incoherent with memory. Another cache reads old value from memory. This demonstrates why cache coherency is needed.
Este repositório foi criado para armazenar códigos feitos durante o andamento da cadeira de Circuitos lógicos II do curso de Engenharia de Computação da UFPB. Todos os códigos foram desenvolvidos utilizando system verilog.
Verification of spi protocol
RTL detects a packet and performs LED on/off based on command bytes in packet. It has a serial TX/RX bus to communicate. It drives RX with TX bytes after link_stable is achieved(Align Markers detection). Send 5 successive AMs to assert link_stable.
System Verilog using Functional Verification
Verification i2c communication protocol
IceCream for SystemVerilog: Never use $display and `uvm_info to debug SystemVerilog again.
This example .BMP generator and ASCII script file reader can be adapted to test code such as pixel drawing algorithms, picture filters, and make use of a source ascii file to drive the inputs of your .sv DUT module while offering logging of the results, and executing the list of commands in order.
This repository is a simple framework for verifying a memory using SystemVerilog on QuestaSim.
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