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ammarmalik17 / Verilog_Adders

Star 1

This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.

circuit-simulation verilog-hdl test-bench half-adder hardware-description-language digital-electronics full-adder verilog-project vlsi-design rtl-design arithmetic-operations fpga-verilog logic-circuit-design behavioral-modeling 4-bit-adder verilog-adders gate-level-design dataflow-design digital-circuit-simulation hdl-coding
  • Updated Aug 24, 2024
  • Verilog

BrianHGinc / SystemVerilog-TestBench-BPM-picture-generator

Star 5

This example .BMP generator and ASCII script file reader can be adapted to test code such as pixel drawing algorithms, picture filters, and make use of a source ascii file to drive the inputs of your .sv DUT module while offering logging of the results, and executing the list of commands in order.

verilog systemverilog hdl test-bench systemverilog-simulation verilog-tb verilog-testbenches systemverilog-test-bench
  • Updated Sep 5, 2021
  • SystemVerilog

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