possible typos in one of your zsim articles

[Z-Y00]

Hi ziqi,
Thanks a lot for your great blog, it helps me a lot.
I found one possible typo in your blog here.

When a parent event finishes execution, child events will be notified after an extra preDelay cycles after the parent completion cycle. When all parents of a child event is completed, the child event will be enqueued after an extra postDelay cycle delay.

Then you wrote

The children nodes are notified at cycle doneCycle + postDelay, as discussed above. 

Thanks~!

[Z-Y00]

Also, the

 recursively incoke the parentDone() function 

maybe a typo

[Z-Y00]

overly complicated doe to optimization

should be due?

[Z-Y00]

also

we use the zll clock ather than the logical core clock

might be rather?

[Z-Y00]

Also, for

The slab allocator is implemented in file phase_slab_alloc.h.

Which file are you referring to?
I only found this one https://github.com/s5z/zsim/blob/master/src/slab_alloc.h

Are you using an inside version of zsim ? I'm just a little bit curious.