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1. RISCV-32I-Single-Cycle-Processor RISCV-32I-Single-Cycle-Processor Public

   Implementation of RISCV32I Single Cycle Architecture consisting of six base instructions (R, I, B, S, J, U).

   SystemVerilog 6 2

2. RV32I-M-Extension-with-5-Staged-Pipelined-Processor- RV32I-M-Extension-with-5-Staged-Pipelined-Processor- Public

   This repo contains the M Extension of the RV32I 5 stage pipelined Processor

   Assembly 2

3. RISCV-32I-5-Stage-Pipelined-Processor RISCV-32I-5-Stage-Pipelined-Processor Public

   RISC-V-32I-5-stage-Pipelined-Processor

   SystemVerilog 1 2

4. Implmentation-of-Wiscon-Shell-WISH Implmentation-of-Wiscon-Shell-WISH Public

   Forked from YazanHussnain/Implmentation-of-Wiscon-Shell-WISH

   The Wiscon Shell ( WISH ) is a shell that I implemented in C as part of the ostep-projects assignment. WISH provides users with a set of built-in functions and allows them to execute external progr…

   C 1

5. AMBA-AHB3-Lite-Slave-Protocol-Verification- AMBA-AHB3-Lite-Slave-Protocol-Verification- Public

   This repo contains the verification of AMBA AHB3 lite slave protcol verification using system verilog

   SystemVerilog 1

6. Compliance-Testing-RV32I Compliance-Testing-RV32I Public

   This Repo contains the complianced testing of RV32I

   SystemVerilog