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fix targets order and names
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Co-authored-by: Andrea Bocci <fwyzard@gmail.com>
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@AuroraPerego @fwyzard
AuroraPerego and fwyzard authored Sep 19, 2024
1 parent f44a981 commit 228aac2
Showing 1 changed file with 19 additions and 19 deletions.
38 changes: 19 additions & 19 deletions include/alpaka/kernel/SyclSubgroupSize.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -16,22 +16,21 @@
(__SYCL_TARGET_INTEL_GPU_AML__) || /* Amber Lake Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_CML__) || /* Comet Lake Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_ICLLP__) || /* Ice Lake Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_EHL__) || /* Elkhart Lake or Jasper Lake Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_TGLLP__) || /* Tiger Lake Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_RKL__) || /* Rocket Lake Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_ADL_S__) || /* Alder Lake S or Raptor Lake Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_ADL_S__) || /* Alder Lake S or Raptor Lake S Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_ADL_P__) || /* Alder Lake P Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_ADL_N__) || /* Alder Lake N Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_DG1__) || /* DG1 Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_ACM_G10__) || /* Alchemist G10 Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_ACM_G11__) || /* Alchemist G11 Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_ACM_G12__) || /* Alchemist G12 Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_MTL_U__) || /* Meteor Lake U/S or Arrow Lake U/S Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_MTL_H__) || /* Meteor Lake H Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_ARL_H__) || /* Arrow Lake H Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_BMG_G21__) || /* Battlemage G21 Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_EHL__) || /* Elkhart Lake or Jasper Lake Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_LNL_M__) || /* Lunar Lake Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_MTL_H__) || /* Meteor Lake H Intel graphics architecture */ \
(__SYCL_TARGET_INTEL_GPU_MTL_U__) /* Meteor Lake U/S or Arrow Lake U/S Intel graphics architecture */

(__SYCL_TARGET_INTEL_GPU_LNL_M__) /* Lunar Lake Intel graphics architecture */

# define SYCL_SUBGROUP_SIZE (8 | 16 | 32)

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(__SYCL_TARGET_AMD_GPU_GFX904__) || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX906__) || /* AMD GCN 5.1 Vega II architecture (gfx 9.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX908__) || /* AMD CDNA 1.0 Arcturus architecture (gfx 9.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX909__) || /* AMD GCN 5.0 Raven 2 architecture (gfx 9.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX90A__) || /* AMD CDNA 2.0 Aldebaran architecture (gfx 9.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX909__) || /* AMD GCN 5.0 Vega architecture (gfx 9.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX90C__) || /* AMD GCN 5.1 Vega 7 architecture (gfx 9.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX940__) || /* AMD CDNA 3.0 Instinct architecture (gfx 9.4) */ \
(__SYCL_TARGET_AMD_GPU_GFX941__) || /* AMD CDNA 3.0 Instinct architecture (gfx 9.4) */ \
(__SYCL_TARGET_AMD_GPU_GFX942__) /* AMD CDNA 3.0 Instinct architecture (gfx 9.4) */
(__SYCL_TARGET_AMD_GPU_GFX90C__) || /* AMD GCN 5.1 Renoir architecture (gfx 9.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX940__) || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \
(__SYCL_TARGET_AMD_GPU_GFX941__) || /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */ \
(__SYCL_TARGET_AMD_GPU_GFX942__) /* AMD CDNA 3.0 Aqua Vanjaram architecture (gfx 9.4) */

# define SYCL_SUBGROUP_SIZE (64)

Expand All @@ -90,16 +89,17 @@
(__SYCL_TARGET_AMD_GPU_GFX1030__) || /* AMD RDNA 2.0 Navi 21 architecture (gfx 10.3) */ \
(__SYCL_TARGET_AMD_GPU_GFX1031__) || /* AMD RDNA 2.0 Navi 22 architecture (gfx 10.3) */ \
(__SYCL_TARGET_AMD_GPU_GFX1032__) || /* AMD RDNA 2.0 Navi 23 architecture (gfx 10.3) */ \
(__SYCL_TARGET_AMD_GPU_GFX1033__) || /* AMD RDNA 2.0 Van Gogh architecture (gfx 10.3) */ \
(__SYCL_TARGET_AMD_GPU_GFX1034__) || /* AMD RDNA 2.0 Navi 24 architecture (gfx 10.3) */ \
(__SYCL_TARGET_AMD_GPU_GFX1035__) || /* AMD RDNA 2.0 Navi 24 architecture (gfx 10.3) */ \
(__SYCL_TARGET_AMD_GPU_GFX1036__) || /* AMD RDNA 2.0 Navi 24 architecture (gfx 10.3) */ \
(__SYCL_TARGET_AMD_GPU_GFX1100__) || /* AMD RDNA 3.0 Navi 33 architecture (gfx 11.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX1101__) || /* AMD RDNA 3.0 Navi 33 architecture (gfx 11.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX1035__) || /* AMD RDNA 2.0 Rembrandt Mobile architecture (gfx 10.3) */ \
(__SYCL_TARGET_AMD_GPU_GFX1036__) || /* AMD RDNA 2.0 Raphael architecture (gfx 10.3) */ \
(__SYCL_TARGET_AMD_GPU_GFX1100__) || /* AMD RDNA 3.0 Navi 31 architecture (gfx 11.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX1101__) || /* AMD RDNA 3.0 Navi 32 architecture (gfx 11.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX1102__) || /* AMD RDNA 3.0 Navi 33 architecture (gfx 11.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX1103__) || /* AMD RDNA 3.0 Navi 33 architecture (gfx 11.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX1150__) || /* AMD RDNA 3.5 Navi 33 architecture (gfx 11.5) */ \
(__SYCL_TARGET_AMD_GPU_GFX1151__) || /* AMD RDNA 3.5 Navi 33 architecture (gfx 11.5) */ \
(__SYCL_TARGET_AMD_GPU_GFX1200__) || /* AMD RDNA 4.0 Navi 48 architecture (gfx 12.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX1103__) || /* AMD RDNA 3.0 Phoenix mobile architecture (gfx 11.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX1150__) || /* AMD RDNA 3.5 Strix Point architecture (gfx 11.5) */ \
(__SYCL_TARGET_AMD_GPU_GFX1151__) || /* AMD RDNA 3.5 Strix Halo architecture (gfx 11.5) */ \
(__SYCL_TARGET_AMD_GPU_GFX1200__) || /* AMD RDNA 4.0 Navi 44 architecture (gfx 12.0) */ \
(__SYCL_TARGET_AMD_GPU_GFX1201__) /* AMD RDNA 4.0 Navi 48 architecture (gfx 12.0) */

// starting from gfx10, HIP supports only wavefront size 32
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