Commits on Jun 3, 2024

1. Enable hardware stack zeroing. …

   This replaces the software stack zeroing path with offload to a hardware
   engine, when available.  The hardware zeroing pipeline is controlled by
   the ZTOP SCR (currently assumed to be number 27).  This zeroes from the
   top of the capability in ZTOP to the bottom.
   
   We assume that short-lived cross-compartment calls or returns from
   deeply nested calls will result in ranges where each is a subset of
   another, so we try to coalesce.
   
   If we're about to zero a region that is a superset of the current
   zeroing region, we skip it, otherwise we wait for the previous zeroing
   region to finish.  This is a fairly simple approach but was chosen
   because adding a lot of instructions in this path can rapidly offset the
   benefits.
   
   0.3% speedup on Sonata.
   2% speedup on the Ibex SAFE simulator.
   
   The difference here is largely due to the UART at 115,200 b/s being
   *very* slow in comparison to the CPU and so the test suite is mostly
   waiting to write debug messages.  The simulator UART can write one
   character per cycle.  The allocator portion of the test suite (which
   does a lot of work per message) is around 1% faster.
   
   The test suite crashes on the Arty A7, which may be a bug in the A7
   version but may be a bug in this code and so we shouldn't merge it yet.

   

   davidchisnall committed Jun 3, 2024
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