Wishlist

Things we would like TestRIG to do better:

• Report all bits of a capability write back, not just 64 bits.

• PERMIT_(LOAD|STORE)_CAPABILITY tag stripping vs trapping.

• Always check xCAUSE for traps.

• Check writes to floating point registers (i.e. implement the floating point extension to RVFI that's already been defined by Wolf).

• Generate compressed instructions (extension C). This isn't just about adding extra instructions; some additional plumbing may be needed to feed 16-bit instructions into the system under test.

• At the moment, we test (for example) extension M on its own (not even with base ISA) and then base ISAA+all extensions. It would be useful to test base ISA+a single extension. Alternatively: extension M + some load immediate instructions. We've already got function2 prepReg32 and prepReg64 that could be used.

• Are we testing MRET, SRET and URET?

• The test for all extensions should have a preamble that combines the preambles for all of the extensions being tested. In particular, it should initialize floating point registers if F or D are under test.

• The disassembly of the opcode that TestRig puts in a comment in the test case should use the correct names for the registers (x1 or f1, not r1)

• The TestRIG memory map should include "uncached" memory with some defined peripheral-like behaviour

• Have a "noshrink" directive when saving a trace to a file

• possibly have a richer TestRIG save format that that would include the DII sequence, possible initialisation data, possible expected RVFI trace (allowing for standalone run of implementation without run of oracle), the expected RISC-V configuration

• ShowS style Template concatenation for performance