Comply with CHERI-architecture reserved RISC-V opcodes for tracing.

target/riscv/insn_trans/trans_rvi.c.inc

@@ -284,7 +284,7 @@ static bool trans_slti(DisasContext *ctx, arg_slti *a)
             gen_helper_qemu_log_instr_stop(cpu_env, tpc);
             ctx->base.is_jmp = DISAS_NORETURN;
             break;
-        case 0x30:
+        case 0x2f:
             gen_helper_riscv_log_instr_event(cpu_env, tpc);
             break;
         }