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Memory versioning implementation (do not merge) #143

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@rmn30 rmn30 commented Apr 27, 2021

This PR is for discussion of qemu memory versioning implementation -- I do not necessarily expect it to be merged and certainly not in the current state.

The extensions are specified in a PRs to the architecture document and on mem_versions branch of the sail model.

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rmn30 commented Apr 27, 2021

Notes from the commit message:

This is an initial implementation and is an incomplete and slow notably:

  1. version checks are performed during capability permissions checks
    and (I think) walk the page table each time rather than using the soft TLB as
    they should.
  2. Loads and stores via DDC will throw an exception if DDC is versioned.
  3. Version violations throw a capability exception and not an MMU fault
  4. No system register or PTE bits yet.
  5. Probably buggy.

It is incomplete and may be slow / buggy notably:

1) version checks are performed during capability permissions checks, using the iotlb to cache a pointer to version memory, which is allocated alongside tag memory in cheri_tagmem.c. It uses one byte per version instead of a nibble like the ARM MTE so a bit space inefficient.
2) Loads and stores via DDC will throw an exception if DDC is versioned.
3) No system register.

Note that this is the result of rebasing against upstream and simultaneously squashing the previous branch. There had been quite a lot of upstream changes with conflicts and some not very interesting history so it turned out to be easier that way.
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