arm: aspeed: Update secure memory layout

Update the TZDRAM region based on the 1GB DRAM space of
Aspeed AST2600/AST2700 EVBs.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>

core/arch/arm/plat-aspeed/conf.mk

@@ -14,8 +14,8 @@ CFG_NUM_THREADS ?= $(CFG_TEE_CORE_NB_CORE)
 CFG_DRAM_BASE ?= 0x80000000
 CFG_DRAM_SIZE ?= 0x40000000
 
-CFG_TZDRAM_START ?= 0x88000000
-CFG_TZDRAM_SIZE ?= 0x01000000
+CFG_TZDRAM_START ?= 0xb0000000
+CFG_TZDRAM_SIZE ?= 0x1000000
 
 CFG_CORE_RESERVED_SHM ?= n
 else ifeq ($(PLATFORM_FLAVOR),ast2700)
@@ -34,10 +34,10 @@ $(call force,CFG_LPAE_ADDR_SPACE_BITS,36)
 CFG_NUM_THREADS ?= $(CFG_TEE_CORE_NB_CORE)
 
 CFG_DRAM_BASE ?= 0x400000000
-CFG_DRAM_SIZE ?= 0x400000000
+CFG_DRAM_SIZE ?= 0x40000000
 
-CFG_TZDRAM_START ?= 0x400400000
-CFG_TZDRAM_SIZE ?= 0x400000
+CFG_TZDRAM_START ?= 0x430080000
+CFG_TZDRAM_SIZE ?= 0x1000000
 
 CFG_CORE_RESERVED_SHM ?= n