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[RISCV] Mark pointer masking extensions as non-experimental (llvm#113618
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)

These extensions were ratified very recently.

<https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154732/Ratified+Extensions>

I've ensured we have definitions for all extensions in the document
<https://drive.google.com/file/d/159QffOTbi3EEbdkKndYRZ2c46D25ZLmO/view?usp=drive_link>.
There are no additional CSRs.
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@asb
asb authored Oct 25, 2024
1 parent 2d26ef0 commit 2c0b348
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10 changes: 5 additions & 5 deletions clang/test/Driver/print-supported-extensions-riscv.c
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Expand Up @@ -120,6 +120,8 @@
// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
// CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode)
// CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
// CHECK-NEXT: smrnmi 1.0 'Smrnmi' (Resumable Non-Maskable Interrupts)
// CHECK-NEXT: smstateen 1.0 'Smstateen' (Machine-mode view of the state-enable extension)
// CHECK-NEXT: ssaia 1.0 'Ssaia' (Advanced Interrupt Architecture Supervisor Level)
Expand All @@ -128,13 +130,16 @@
// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering)
// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)
// CHECK-NEXT: sscsrind 1.0 'Sscsrind' (Indirect CSR Access Supervisor Level)
// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
// CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers)
// CHECK-NEXT: ssstateen 1.0 'Ssstateen' (Supervisor-mode view of the state-enable extension)
// CHECK-NEXT: ssstrict 1.0 'Ssstrict' (No non-conforming extensions are present)
// CHECK-NEXT: sstc 1.0 'Sstc' (Supervisor-mode timer interrupts)
// CHECK-NEXT: sstvala 1.0 'Sstvala' (stval provides all needed values)
// CHECK-NEXT: sstvecd 1.0 'Sstvecd' (stvec supports Direct mode)
// CHECK-NEXT: ssu64xl 1.0 'Ssu64xl' (UXLEN=64 supported)
// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)
// CHECK-NEXT: svade 1.0 'Svade' (Raise exceptions on improper A/D bits)
// CHECK-NEXT: svadu 1.0 'Svadu' (Hardware A/D updates)
// CHECK-NEXT: svbare 1.0 'Svbare' $(satp mode Bare supported)
Expand Down Expand Up @@ -177,12 +182,7 @@
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
// CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode)
// CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)
// CHECK-EMPTY:
// CHECK-NEXT: Supported Profiles
// CHECK-NEXT: rva20s64
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2 changes: 1 addition & 1 deletion clang/test/Driver/riscv-profiles.c
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Expand Up @@ -195,7 +195,7 @@
// RVA23S64: "-target-feature" "+ssccptr"
// RVA23S64: "-target-feature" "+sscofpmf"
// RVA23S64: "-target-feature" "+sscounterenw"
// RVA23S64: "-target-feature" "+experimental-ssnpm"
// RVA23S64: "-target-feature" "+ssnpm"
// RVA23S64: "-target-feature" "+ssstateen"
// RVA23S64: "-target-feature" "+sstc"
// RVA23S64: "-target-feature" "+sstvala"
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16 changes: 8 additions & 8 deletions clang/test/Preprocessor/riscv-target-features.c
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Expand Up @@ -1719,10 +1719,10 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
// CHECK-ZICFISS-EXT: __riscv_zicfiss 1000000{{$}}

// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: %clang --target=riscv32 \
// RUN: -march=rv32i_ssnpm1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64i_ssnpm1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
// CHECK-SSNPM-EXT: __riscv_ssnpm 1000000{{$}}
Expand All @@ -1735,26 +1735,26 @@
// RUN: -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
// CHECK-SMNPM-EXT: __riscv_smnpm 1000000{{$}}

// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: %clang --target=riscv32 \
// RUN: -march=rv32i_smmpm1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64i_smmpm1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
// CHECK-SMMPM-EXT: __riscv_smmpm 1000000{{$}}

// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: %clang --target=riscv32 \
// RUN: -march=rv32i_sspm1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64i_sspm1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
// CHECK-SSPM-EXT: __riscv_sspm 1000000{{$}}

// RUN: %clang --target=riscv32 -menable-experimental-extensions \
// RUN: %clang --target=riscv32 \
// RUN: -march=rv32i_supm1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
// RUN: %clang --target=riscv64 \
// RUN: -march=rv64i_supm1p0 -E -dM %s \
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
// CHECK-SUPM-EXT: __riscv_supm 1000000{{$}}
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8 changes: 5 additions & 3 deletions llvm/docs/RISCVUsage.rst
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Expand Up @@ -129,6 +129,8 @@ on support follow.
``Smcdeleg`` Supported
``Smcsrind`` Supported
``Smepmp`` Supported
``Smmpm`` Supported
``Smnpm`` Supported
``Smrnmi`` Assembly Support
``Smstateen`` Assembly Support
``Ssaia`` Supported
Expand All @@ -137,13 +139,16 @@ on support follow.
``Sscofpmf`` Assembly Support
``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Sscsrind`` Supported
``Ssnpm`` Supported
``Sspm`` Supported
``Ssqosid`` Assembly Support
``Ssstateen`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Ssstrict`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Sstc`` Assembly Support
``Sstvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Sstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Ssu64xl`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Supm`` Supported
``Svade`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
``Svadu`` Assembly Support
``Svbare`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
Expand Down Expand Up @@ -308,9 +313,6 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp

The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.

``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm``
LLVM implements the `v1.0.0-rc2 specification <https://github.com/riscv/riscv-j-extension/releases/tag/pointer-masking-v1.0.0-rc2>`__.

``experimental-zalasr``
LLVM implements the `0.0.5 draft specification <https://github.com/mehnadnerd/riscv-zalasr>`__.

Expand Down
2 changes: 2 additions & 0 deletions llvm/docs/ReleaseNotes.md
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Expand Up @@ -171,6 +171,8 @@ Changes to the RISC-V Backend
* Added `Smctr` and `Ssctr` extensions.
* `-mcpu=syntacore-scr7` was added.
* The `Zacas` extension is no longer marked as experimental.
* The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
are no longer marked as experimental.

Changes to the WebAssembly Backend
----------------------------------
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20 changes: 10 additions & 10 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -1035,33 +1035,33 @@ def FeatureStdExtSvpbmt
// privilege mode (U-mode), and for VS- and VU-modes if the H extension is
// present.
def FeatureStdExtSsnpm
: RISCVExperimentalExtension<"ssnpm", 1, 0,
"'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;
: RISCVExtension<"ssnpm", 1, 0,
"'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;

// A machine-level extension that provides pointer masking for the next lower
// privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).
def FeatureStdExtSmnpm
: RISCVExperimentalExtension<"smnpm", 1, 0,
"'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)">;
: RISCVExtension<"smnpm", 1, 0,
"'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)">;

// A machine-level extension that provides pointer masking for M-mode.
def FeatureStdExtSmmpm
: RISCVExperimentalExtension<"smmpm", 1, 0,
"'Smmpm' (Machine-level Pointer Masking for M-mode)">;
: RISCVExtension<"smmpm", 1, 0,
"'Smmpm' (Machine-level Pointer Masking for M-mode)">;

// An extension that indicates that there is pointer-masking support available
// in supervisor mode, with some facility provided in the supervisor execution
// environment to control pointer masking.
def FeatureStdExtSspm
: RISCVExperimentalExtension<"sspm", 1, 0,
"'Sspm' (Indicates Supervisor-mode Pointer Masking)">;
: RISCVExtension<"sspm", 1, 0,
"'Sspm' (Indicates Supervisor-mode Pointer Masking)">;

// An extension that indicates that there is pointer-masking support available
// in user mode, with some facility provided in the application execution
// environment to control pointer masking.
def FeatureStdExtSupm
: RISCVExperimentalExtension<"supm", 1, 0,
"'Supm' (Indicates User-mode Pointer Masking)">;
: RISCVExtension<"supm", 1, 0,
"'Supm' (Indicates User-mode Pointer Masking)">;

def FeatureStdExtSmctr
: RISCVExperimentalExtension<"smctr", 1, 0,
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -129,11 +129,11 @@
; RUN: llc -mtriple=riscv32 -mattr=+a,+zabha %s -o - | FileCheck --check-prefix=RV32ZABHA %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbc32e %s -o - | FileCheck --check-prefix=RV32ZVBC32E %s
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkgs %s -o - | FileCheck --check-prefix=RV32ZVKGS %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssnpm %s -o - | FileCheck --check-prefix=RV32SSNPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smnpm %s -o - | FileCheck --check-prefix=RV32SMNPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
; RUN: llc -mtriple=riscv32 -mattr=+ssnpm %s -o - | FileCheck --check-prefix=RV32SSNPM %s
; RUN: llc -mtriple=riscv32 -mattr=+smnpm %s -o - | FileCheck --check-prefix=RV32SMNPM %s
; RUN: llc -mtriple=riscv32 -mattr=+smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
; RUN: llc -mtriple=riscv32 -mattr=+sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
; RUN: llc -mtriple=riscv32 -mattr=+supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV32SMCTR %s
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV32SSCTR %s

Expand Down Expand Up @@ -272,11 +272,11 @@
; RUN: llc -mtriple=riscv64 -mattr=+a,+zabha %s -o - | FileCheck --check-prefix=RV64ZABHA %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbc32e %s -o - | FileCheck --check-prefix=RV64ZVBC32E %s
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkgs %s -o - | FileCheck --check-prefix=RV64ZVKGS %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssnpm %s -o - | FileCheck --check-prefix=RV64SSNPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smnpm %s -o - | FileCheck --check-prefix=RV64SMNPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
; RUN: llc -mtriple=riscv64 -mattr=+ssnpm %s -o - | FileCheck --check-prefix=RV64SSNPM %s
; RUN: llc -mtriple=riscv64 -mattr=+smnpm %s -o - | FileCheck --check-prefix=RV64SMNPM %s
; RUN: llc -mtriple=riscv64 -mattr=+smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
; RUN: llc -mtriple=riscv64 -mattr=+sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
; RUN: llc -mtriple=riscv64 -mattr=+supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s

Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rvv/pr107950.ll
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Expand Up @@ -26,5 +26,5 @@ entry:
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
declare <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr>, i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i32>) #1

attributes #0 = { "target-features"="+64bit,+d,+f,+relax,+v,+xsifivecdiscarddlone,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a,-b,-c,-e,-experimental-smctr,-experimental-smmpm,-experimental-smnpm,-experimental-ssctr,-experimental-ssnpm,-experimental-sspm,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-h,-m,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
attributes #0 = { "target-features"="+64bit,+d,+f,+relax,+v,+xsifivecdiscarddlone,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a,-b,-c,-e,-experimental-smctr,-smmpm,-smnpm,-experimental-ssctr,-ssnpm,-sspm,-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-h,-m,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }
10 changes: 5 additions & 5 deletions llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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Expand Up @@ -1065,6 +1065,8 @@ R"(All available -march extensions for RISC-V
smcdeleg 1.0
smcsrind 1.0
smepmp 1.0
smmpm 1.0
smnpm 1.0
smrnmi 1.0
smstateen 1.0
ssaia 1.0
Expand All @@ -1073,13 +1075,16 @@ R"(All available -march extensions for RISC-V
sscofpmf 1.0
sscounterenw 1.0
sscsrind 1.0
ssnpm 1.0
sspm 1.0
ssqosid 1.0
ssstateen 1.0
ssstrict 1.0
sstc 1.0
sstvala 1.0
sstvecd 1.0
ssu64xl 1.0
supm 1.0
svade 1.0
svadu 1.0
svbare 1.0
Expand Down Expand Up @@ -1122,12 +1127,7 @@ Experimental extensions
zvbc32e 0.7
zvkgs 0.7
smctr 1.0
smmpm 1.0
smnpm 1.0
ssctr 1.0
ssnpm 1.0
sspm 1.0
supm 1.0
Supported Profiles
rva20s64
Expand Down

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