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[AArch64] Add assembly/disassembly for SVE zeroing int-float conversi…
…ons (llvm#113605) This patch adds assembly/disassembly for the following predicated SVE2.2 instructions - SCVTF (zeroing) - UCVTF (zeroing) - FCVTZS (zeroing) - FCVTZU (zeroing) - FLOGB (zeroing) - In accordance with: https://developer.arm.com/documentation/ddi0602/latest/
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s | ||
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fcvtzs z0.h, p0/z, z0.s | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: fcvtzs z0.h, p0/z, z0.s | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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fcvtzs z0.h, p0/z, z0.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: fcvtzs z0.h, p0/z, z0.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// ------------------------------------------------------------------------- // | ||
// Invalid predicate | ||
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fcvtzs z0.h, p8/z, z0.h | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) | ||
// CHECK-NEXT: fcvtzs z0.h, p8/z, z0.h | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// --------------------------------------------------------------------------// | ||
// Negative tests for instructions that are incompatible with movprfx | ||
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movprfx z0.d, p0/z, z7.d | ||
fcvtzs z0.d, p0/z, z3.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov | ||
// CHECK-NEXT: fcvtzs z0.d, p0/z, z3.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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movprfx z0, z7 | ||
fcvtzs z0.d, p0/z, z3.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov | ||
// CHECK-NEXT: fcvtzs z0.d, p0/z, z3.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ | ||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ | ||
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ | ||
// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN | ||
// Disassemble encoding and check the re-encoding (-show-encoding) matches. | ||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ | ||
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ | ||
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
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// convert from half | ||
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fcvtzs z0.h, p0/z, z0.h // 01100100-01011110-11000000-00000000 | ||
// CHECK-INST: fcvtzs z0.h, p0/z, z0.h | ||
// CHECK-ENCODING: [0x00,0xc0,0x5e,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 645ec000 <unknown> | ||
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fcvtzs z23.s, p3/z, z13.h // 01100100-01011111-10001101-10110111 | ||
// CHECK-INST: fcvtzs z23.s, p3/z, z13.h | ||
// CHECK-ENCODING: [0xb7,0x8d,0x5f,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 645f8db7 <unknown> | ||
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fcvtzs z31.d, p7/z, z31.h // 01100100-01011111-11011111-11111111 | ||
// CHECK-INST: fcvtzs z31.d, p7/z, z31.h | ||
// CHECK-ENCODING: [0xff,0xdf,0x5f,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 645fdfff <unknown> | ||
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// convert from single | ||
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fcvtzs z0.s, p0/z, z0.s // 01100100-10011111-10000000-00000000 | ||
// CHECK-INST: fcvtzs z0.s, p0/z, z0.s | ||
// CHECK-ENCODING: [0x00,0x80,0x9f,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 649f8000 <unknown> | ||
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fcvtzs z21.d, p5/z, z10.s // 01100100-11011111-10010101-01010101 | ||
// CHECK-INST: fcvtzs z21.d, p5/z, z10.s | ||
// CHECK-ENCODING: [0x55,0x95,0xdf,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 64df9555 <unknown> | ||
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// convert from double | ||
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fcvtzs z23.s, p3/z, z13.d // 01100100-11011110-10001101-10110111 | ||
// CHECK-INST: fcvtzs z23.s, p3/z, z13.d | ||
// CHECK-ENCODING: [0xb7,0x8d,0xde,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 64de8db7 <unknown> | ||
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fcvtzs z31.d, p7/z, z31.d // 01100100-11011111-11011111-11111111 | ||
// CHECK-INST: fcvtzs z31.d, p7/z, z31.d | ||
// CHECK-ENCODING: [0xff,0xdf,0xdf,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 64dfdfff <unknown> |
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s | ||
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fcvtzu z0.h, p0/z, z0.s | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: fcvtzu z0.h, p0/z, z0.s | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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fcvtzu z0.h, p0/z, z0.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: fcvtzu z0.h, p0/z, z0.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// ------------------------------------------------------------------------- // | ||
// Invalid predicate | ||
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fcvtzu z0.h, p8/z, z0.h | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) | ||
// CHECK-NEXT: fcvtzu z0.h, p8/z, z0.h | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// --------------------------------------------------------------------------// | ||
// Negative tests for instructions that are incompatible with movprfx | ||
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movprfx z0.d, p0/z, z7.d | ||
fcvtzu z0.d, p0/z, z3.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov | ||
// CHECK-NEXT: fcvtzu z0.d, p0/z, z3.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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movprfx z0, z7 | ||
fcvtzu z0.d, p0/z, z3.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov | ||
// CHECK-NEXT: fcvtzu z0.d, p0/z, z3.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ | ||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ | ||
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ | ||
// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN | ||
// Disassemble encoding and check the re-encoding (-show-encoding) matches. | ||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ | ||
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ | ||
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
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// convert from half | ||
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fcvtzu z0.h, p0/z, z0.h // 01100100-01011110-11100000-00000000 | ||
// CHECK-INST: fcvtzu z0.h, p0/z, z0.h | ||
// CHECK-ENCODING: [0x00,0xe0,0x5e,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 645ee000 <unknown> | ||
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fcvtzu z21.s, p5/z, z10.h // 01100100-01011111-10110101-01010101 | ||
// CHECK-INST: fcvtzu z21.s, p5/z, z10.h | ||
// CHECK-ENCODING: [0x55,0xb5,0x5f,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 645fb555 <unknown> | ||
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fcvtzu z23.d, p3/z, z13.h // 01100100-01011111-11101101-10110111 | ||
// CHECK-INST: fcvtzu z23.d, p3/z, z13.h | ||
// CHECK-ENCODING: [0xb7,0xed,0x5f,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 645fedb7 <unknown> | ||
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// convert from single | ||
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fcvtzu z21.s, p5/z, z10.s // 01100100-10011111-10110101-01010101 | ||
// CHECK-INST: fcvtzu z21.s, p5/z, z10.s | ||
// CHECK-ENCODING: [0x55,0xb5,0x9f,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 649fb555 <unknown> | ||
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fcvtzu z31.d, p7/z, z31.s // 01100100-11011111-10111111-11111111 | ||
// CHECK-INST: fcvtzu z31.d, p7/z, z31.s | ||
// CHECK-ENCODING: [0xff,0xbf,0xdf,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 64dfbfff <unknown> | ||
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// convert from double | ||
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fcvtzu z0.s, p0/z, z0.d // 01100100-11011110-10100000-00000000 | ||
// CHECK-INST: fcvtzu z0.s, p0/z, z0.d | ||
// CHECK-ENCODING: [0x00,0xa0,0xde,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 64dea000 <unknown> | ||
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fcvtzu z31.d, p7/z, z31.d // 01100100-11011111-11111111-11111111 | ||
// CHECK-INST: fcvtzu z31.d, p7/z, z31.d | ||
// CHECK-ENCODING: [0xff,0xff,0xdf,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 64dfffff <unknown> |
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s | ||
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// --------------------------------------------------------------------------// | ||
// Invalid element width | ||
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flogb z0.b, p0/z, z0.b | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: flogb z0.b, p0/z, z0.b | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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flogb z0.h, p0/z, z0.s | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: flogb z0.h, p0/z, z0.s | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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flogb z0.s, p0/z, z0.h | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: flogb z0.s, p0/z, z0.h | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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flogb z0.d, p0/z, z0.s | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: flogb z0.d, p0/z, z0.s | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// ------------------------------------------------------------------------- // | ||
// Invalid predicate | ||
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flogb z0.h, p8/z, z0.h | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) | ||
// CHECK-NEXT: flogb z0.h, p8/z, z0.h | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// --------------------------------------------------------------------------// | ||
// Negative tests for instructions that are incompatible with movprfx | ||
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movprfx z0.d, p0/z, z7.d | ||
flogb z0.d, p0/z, z3.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov | ||
// CHECK-NEXT: flogb z0.d, p0/z, z3.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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movprfx z0, z7 | ||
flogb z0.d, p0/z, z3.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov | ||
// CHECK-NEXT: flogb z0.d, p0/z, z3.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
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@@ -0,0 +1,33 @@ | ||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p2 < %s \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ | ||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ | ||
// RUN: | llvm-objdump -d --mattr=+sve2p2 - | FileCheck %s --check-prefix=CHECK-INST | ||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p2 < %s \ | ||
// RUN: | llvm-objdump -d --mattr=-sve - | FileCheck %s --check-prefix=CHECK-UNKNOWN | ||
// Disassemble encoding and check the re-encoding (-show-encoding) matches. | ||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 < %s \ | ||
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ | ||
// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p2 -disassemble -show-encoding \ | ||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST | ||
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flogb z0.h, p0/z, z0.h // 01100100-00011110-10100000-00000000 | ||
// CHECK-INST: flogb z0.h, p0/z, z0.h | ||
// CHECK-ENCODING: [0x00,0xa0,0x1e,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 641ea000 <unknown> | ||
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flogb z23.s, p3/z, z13.s // 01100100-00011110-11001101-10110111 | ||
// CHECK-INST: flogb z23.s, p3/z, z13.s | ||
// CHECK-ENCODING: [0xb7,0xcd,0x1e,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 641ecdb7 <unknown> | ||
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flogb z31.d, p7/z, z31.d // 01100100-00011110-11111111-11111111 | ||
// CHECK-INST: flogb z31.d, p7/z, z31.d | ||
// CHECK-ENCODING: [0xff,0xff,0x1e,0x64] | ||
// CHECK-ERROR: instruction requires: sme2p2 or sve2p2 | ||
// CHECK-UNKNOWN: 641effff <unknown> |
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@@ -0,0 +1,34 @@ | ||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p2 2>&1 < %s| FileCheck %s | ||
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scvtf z0.s, p0/z, z0.h | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: scvtf z0.s, p0/z, z0.h | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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scvtf z0.d, p0/z, z0.h | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width | ||
// CHECK-NEXT: scvtf z0.d, p0/z, z0.h | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// ------------------------------------------------------------------------- // | ||
// Invalid predicate | ||
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scvtf z0.h, p8/z, z0.h | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix) | ||
// CHECK-NEXT: scvtf z0.h, p8/z, z0.h | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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// --------------------------------------------------------------------------// | ||
// Negative tests for instructions that are incompatible with movprfx | ||
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movprfx z0.d, p0/z, z7.d | ||
scvtf z0.d, p0/z, z3.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov | ||
// CHECK-NEXT: scvtf z0.d, p0/z, z3.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: | ||
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movprfx z0, z7 | ||
scvtf z0.d, p0/z, z3.d | ||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx, suggest replacing movprfx with mov | ||
// CHECK-NEXT: scvtf z0.d, p0/z, z3.d | ||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}: |
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