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Merge pull request #4134 from Sonicadvance1/move_jit
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JIT: Moves Arm64 JIT up one folder
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@lioncash
lioncash authored Oct 27, 2024
2 parents 992d6e8 + b31e4a3 commit 079e70f
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Showing 15 changed files with 27 additions and 45 deletions.
22 changes: 11 additions & 11 deletions FEXCore/Source/CMakeLists.txt
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Expand Up @@ -105,17 +105,17 @@ set (SRCS
Interface/Core/ArchHelpers/Arm64Emitter.cpp
Interface/Core/Dispatcher/Dispatcher.cpp
Interface/Core/Interpreter/Fallbacks/InterpreterFallbacks.cpp
Interface/Core/JIT/Arm64/JIT.cpp
Interface/Core/JIT/Arm64/ALUOps.cpp
Interface/Core/JIT/Arm64/AtomicOps.cpp
Interface/Core/JIT/Arm64/BranchOps.cpp
Interface/Core/JIT/Arm64/ConversionOps.cpp
Interface/Core/JIT/Arm64/EncryptionOps.cpp
Interface/Core/JIT/Arm64/MemoryOps.cpp
Interface/Core/JIT/Arm64/MiscOps.cpp
Interface/Core/JIT/Arm64/MoveOps.cpp
Interface/Core/JIT/Arm64/VectorOps.cpp
Interface/Core/JIT/Arm64/Arm64Relocations.cpp
Interface/Core/JIT/JIT.cpp
Interface/Core/JIT/ALUOps.cpp
Interface/Core/JIT/AtomicOps.cpp
Interface/Core/JIT/BranchOps.cpp
Interface/Core/JIT/ConversionOps.cpp
Interface/Core/JIT/EncryptionOps.cpp
Interface/Core/JIT/MemoryOps.cpp
Interface/Core/JIT/MiscOps.cpp
Interface/Core/JIT/MoveOps.cpp
Interface/Core/JIT/VectorOps.cpp
Interface/Core/JIT/Arm64Relocations.cpp
Interface/Core/X86Tables/BaseTables.cpp
Interface/Core/X86Tables/DDDTables.cpp
Interface/Core/X86Tables/H0F38Tables.cpp
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4 changes: 2 additions & 2 deletions FEXCore/Source/Interface/Core/Core.cpp
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Expand Up @@ -9,14 +9,14 @@ desc: Glues Frontend, OpDispatcher and IR Opts & Compilation, LookupCache, Dispa
*/

#include <cstdint>
#include "Interface/Core/ArchHelpers//Arm64Emitter.h"
#include "Interface/Core/ArchHelpers/Arm64Emitter.h"
#include "Interface/Core/LookupCache.h"
#include "Interface/Core/CPUBackend.h"
#include "Interface/Core/CPUID.h"
#include "Interface/Core/Frontend.h"
#include "Interface/Core/ObjectCache/ObjectCacheService.h"
#include "Interface/Core/OpcodeDispatcher.h"
#include "Interface/Core/JIT/JITCore.h"
#include "Interface/Core/JIT/JITClass.h"
#include "Interface/Core/Dispatcher/Dispatcher.h"
#include "Interface/Core/X86Tables/X86Tables.h"
#include "Interface/IR/IR.h"
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2 changes: 1 addition & 1 deletion ...ource/Interface/Core/JIT/Arm64/ALUOps.cpp → FEXCore/Source/Interface/Core/JIT/ALUOps.cpp
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Expand Up @@ -8,7 +8,7 @@ tags: backend|arm64
#include "CodeEmitter/Emitter.h"
#include "FEXCore/IR/IR.h"
#include "Interface/Context/Context.h"
#include "Interface/Core/JIT/Arm64/JITClass.h"
#include "Interface/Core/JIT/JITClass.h"
#include "Interface/IR/Passes/RegisterAllocationPass.h"

namespace FEXCore::CPU {
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2 changes: 1 addition & 1 deletion ...rface/Core/JIT/Arm64/Arm64Relocations.cpp → ...e/Interface/Core/JIT/Arm64Relocations.cpp
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Expand Up @@ -6,7 +6,7 @@ desc: relocation logic of the arm64 splatter backend
$end_info$
*/
#include "Interface/Context/Context.h"
#include "Interface/Core/JIT/Arm64/JITClass.h"
#include "Interface/Core/JIT/JITClass.h"

#include <FEXCore/Core/Thunks.h>

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2 changes: 1 addition & 1 deletion ...ce/Interface/Core/JIT/Arm64/AtomicOps.cpp → ...e/Source/Interface/Core/JIT/AtomicOps.cpp
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Expand Up @@ -7,7 +7,7 @@ tags: backend|arm64

#include "Interface/Context/Context.h"
#include "Interface/Core/Dispatcher/Dispatcher.h"
#include "Interface/Core/JIT/Arm64/JITClass.h"
#include "Interface/Core/JIT/JITClass.h"

namespace FEXCore::CPU {
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
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2 changes: 1 addition & 1 deletion ...ce/Interface/Core/JIT/Arm64/BranchOps.cpp → ...e/Source/Interface/Core/JIT/BranchOps.cpp
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Expand Up @@ -9,7 +9,7 @@ tags: backend|arm64
#include "FEXCore/IR/IR.h"
#include "Interface/Core/LookupCache.h"

#include "Interface/Core/JIT/Arm64/JITClass.h"
#include "Interface/Core/JIT/JITClass.h"

#include <FEXCore/Core/Thunks.h>
#include <FEXCore/Core/X86Enums.h>
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2 changes: 1 addition & 1 deletion ...nterface/Core/JIT/Arm64/ConversionOps.cpp → ...urce/Interface/Core/JIT/ConversionOps.cpp
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Expand Up @@ -5,7 +5,7 @@ tags: backend|arm64
$end_info$
*/

#include "Interface/Core/JIT/Arm64/JITClass.h"
#include "Interface/Core/JIT/JITClass.h"

namespace FEXCore::CPU {
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
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2 changes: 1 addition & 1 deletion ...nterface/Core/JIT/Arm64/EncryptionOps.cpp → ...urce/Interface/Core/JIT/EncryptionOps.cpp
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Expand Up @@ -5,7 +5,7 @@ tags: backend|arm64
$end_info$
*/

#include "Interface/Core/JIT/Arm64/JITClass.h"
#include "Interface/Core/JIT/JITClass.h"

namespace FEXCore::CPU {
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
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2 changes: 1 addition & 1 deletion ...e/Source/Interface/Core/JIT/Arm64/JIT.cpp → FEXCore/Source/Interface/Core/JIT/JIT.cpp
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Expand Up @@ -16,7 +16,7 @@ desc: Main glue logic of the arm64 splatter backend
#include "Interface/Core/LookupCache.h"

#include "Interface/Core/Dispatcher/Dispatcher.h"
#include "Interface/Core/JIT/Arm64/JITClass.h"
#include "Interface/Core/JIT/JITClass.h"

#include "Interface/IR/Passes/RegisterAllocationPass.h"

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3 changes: 3 additions & 0 deletions ...ource/Interface/Core/JIT/Arm64/JITClass.h → FEXCore/Source/Interface/Core/JIT/JITClass.h
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Expand Up @@ -352,4 +352,7 @@ class Arm64JITCore final : public CPUBackend, public Arm64Emitter {
#undef DEF_OP
};

[[nodiscard]]
fextl::unique_ptr<CPUBackend> CreateArm64JITCore(FEXCore::Context::ContextImpl* ctx, FEXCore::Core::InternalThreadState* Thread);

} // namespace FEXCore::CPU
21 changes: 0 additions & 21 deletions FEXCore/Source/Interface/Core/JIT/JITCore.h
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2 changes: 1 addition & 1 deletion ...ce/Interface/Core/JIT/Arm64/MemoryOps.cpp → ...e/Source/Interface/Core/JIT/MemoryOps.cpp
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Expand Up @@ -9,7 +9,7 @@ tags: backend|arm64
#include "FEXCore/Utils/LogManager.h"
#include "Interface/Context/Context.h"
#include "Interface/Core/CPUID.h"
#include "Interface/Core/JIT/Arm64/JITClass.h"
#include "Interface/Core/JIT/JITClass.h"
#include <FEXCore/Utils/CompilerDefs.h>
#include <FEXCore/Utils/MathUtils.h>

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2 changes: 1 addition & 1 deletion ...urce/Interface/Core/JIT/Arm64/MiscOps.cpp → ...ore/Source/Interface/Core/JIT/MiscOps.cpp
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Expand Up @@ -10,7 +10,7 @@ tags: backend|arm64
#endif

#include "Interface/Context/Context.h"
#include "Interface/Core/JIT/Arm64/JITClass.h"
#include "Interface/Core/JIT/JITClass.h"
#include "FEXCore/Debug/InternalThreadState.h"

#include <FEXCore/Core/SignalDelegator.h>
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2 changes: 1 addition & 1 deletion ...urce/Interface/Core/JIT/Arm64/MoveOps.cpp → ...ore/Source/Interface/Core/JIT/MoveOps.cpp
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Expand Up @@ -5,7 +5,7 @@ tags: backend|arm64
$end_info$
*/

#include "Interface/Core/JIT/Arm64/JITClass.h"
#include "Interface/Core/JIT/JITClass.h"

namespace FEXCore::CPU {
#define DEF_OP(x) void Arm64JITCore::Op_##x(IR::IROp_Header const* IROp, IR::NodeID Node)
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2 changes: 1 addition & 1 deletion ...ce/Interface/Core/JIT/Arm64/VectorOps.cpp → ...e/Source/Interface/Core/JIT/VectorOps.cpp
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Expand Up @@ -6,7 +6,7 @@ tags: backend|arm64
*/

#include "Interface/Core/Dispatcher/Dispatcher.h"
#include "Interface/Core/JIT/Arm64/JITClass.h"
#include "Interface/Core/JIT/JITClass.h"

#include <FEXCore/Utils/MathUtils.h>

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