Implement NZCVSelectV for selection on FPRs

Behaves like NZCVSelect for FPRs.
FEX-Emu · Sep 30, 2024 · d62dd50 · d62dd50
1 parent e902ad5
commit d62dd50
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Showing 3 changed files with 33 additions and 5 deletions.
diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/ALUOps.cpp
@@ -1535,6 +1535,14 @@ DEF_OP(NZCVSelect) {
   }
 }
 
+DEF_OP(NZCVSelectV) {
+  auto Op = IROp->C<IR::IROp_NZCVSelectV>();
+
+  auto cc = MapCC(Op->Cond);
+  const auto SubRegSize = ConvertSubRegSizePair248(IROp);
+  fcsel(SubRegSize.Scalar, GetVReg(Node), GetVReg(Op->TrueVal.ID()), GetVReg(Op->FalseVal.ID()), cc);
+}
+
 DEF_OP(NZCVSelectIncrement) {
   auto Op = IROp->C<IR::IROp_NZCVSelectIncrement>();
 

diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
@@ -1531,13 +1531,27 @@
         ]
       },
       "GPR = NZCVSelect OpSize:#ResultSize, CondClass:$Cond, GPR:$TrueVal, GPR:$FalseVal": {
-        "Desc": ["Select based on value in NZCV flags",
-                 "op:",
-                 "Dest = Cond ? TrueVal : FalseVal"
-                ],
+        "Desc": [
+          "Select based on value in NZCV flags, where TrueVal and FalseVal are both GPRs.",
+          "op:",
+          "Dest = Cond ? TrueVal : FalseVal"
+        ],
         "DestSize": "ResultSize",
         "EmitValidation": [
-          "ResultSize == FEXCore::IR::OpSize::i32Bit || ResultSize == FEXCore::IR::OpSize::i64Bit"
+          "ResultSize == FEXCore::IR::OpSize::i32Bit || ResultSize == FEXCore::IR::OpSize::i64Bit",
+          "WalkFindRegClass($TrueVal) == GPRClass && WalkFindRegClass($FalseVal) == GPRClass"
+        ]
+      },
+      "FPR = NZCVSelectV OpSize:#ResultSize, u8:$ElementSize, CondClass:$Cond, FPR:$TrueVal, FPR:$FalseVal": {
+        "Desc": [
+          "Select based on value in NZCV flags, where TrueVal and FalseVal are both FPRs.",
+          "op:",
+          "Dest = Cond ? TrueVal : FalseVal"
+        ],
+        "DestSize": "ResultSize",
+        "EmitValidation": [
+          "ResultSize == FEXCore::IR::OpSize::i32Bit || ResultSize == FEXCore::IR::OpSize::i64Bit",
+          "WalkFindRegClass($TrueVal) == FPRClass && WalkFindRegClass($FalseVal) == FPRClass"
         ]
       },
       "GPR = NZCVSelectIncrement OpSize:#ResultSize, CondClass:$Cond, GPR:$TrueVal, GPR:$FalseVal": {

diff --git a/FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp b/FEXCore/Source/Interface/IR/Passes/RedundantFlagCalculationElimination.cpp
@@ -319,6 +319,7 @@ constexpr FlagInfo ClassifyConst(IROps Op) {
   case OP_STOREAF: return FlagInfo::Pack({.Write = FLAG_A, .CanEliminate = true});
 
   case OP_NZCVSELECT:
+  case OP_NZCVSELECTV:
   case OP_NZCVSELECTINCREMENT:
   case OP_NEG:
   case OP_CONDJUMP:
@@ -353,6 +354,11 @@ FlagInfo DeadFlagCalculationEliminination::Classify(IROp_Header* IROp) {
     return FlagInfo::Pack({.Read = FlagsForCondClassType(Op->Cond)});
   }
 
+  case OP_NZCVSELECTV: {
+    auto Op = IROp->CW<IR::IROp_NZCVSelectV>();
+    return FlagInfo::Pack({.Read = FlagsForCondClassType(Op->Cond)});
+  }
+
   case OP_NEG: {
     auto Op = IROp->CW<IR::IROp_Neg>();
     return FlagInfo::Pack({.Read = FlagsForCondClassType(Op->Cond)});