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InstCountCI: Update
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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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alyssarosenzweig committed Feb 12, 2024
1 parent 6823236 commit fba5678
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Showing 9 changed files with 948 additions and 1,500 deletions.
323 changes: 108 additions & 215 deletions unittests/InstructionCountCI/Atomics.json

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251 changes: 101 additions & 150 deletions unittests/InstructionCountCI/FlagM/Atomics.json

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527 changes: 221 additions & 306 deletions unittests/InstructionCountCI/FlagM/Primary.json

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177 changes: 86 additions & 91 deletions unittests/InstructionCountCI/FlagM/PrimaryGroup.json
Original file line number Diff line number Diff line change
Expand Up @@ -15,13 +15,13 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"uxtb w27, w4",
"mov w20, #0x1",
"mov x27, x4",
"add w26, w27, #0x1 (1)",
"mov x4, x27",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"bic w20, w26, w27",
"rmif x20, #7, #nzcV"
"lsl w0, w27, #24",
"cmn w0, w20, lsl #24"
]
},
"or al, 1": {
Expand Down Expand Up @@ -93,16 +93,17 @@
]
},
"sub al, 1": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"uxtb w27, w4",
"mov w20, #0x1",
"mov x27, x4",
"sub w26, w27, #0x1 (1)",
"mov x4, x27",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"bic w20, w27, w26",
"rmif x20, #7, #nzcV"
"lsl w0, w27, #24",
"cmp w0, w20, lsl #24",
"cfinv"
]
},
"xor al, 1": {
Expand All @@ -118,26 +119,26 @@
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x80 /7",
"ExpectedArm64ASM": [
"uxtb w27, w4",
"mov w20, #0x1",
"mov x27, x4",
"sub w26, w27, #0x1 (1)",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"bic w20, w27, w26",
"rmif x20, #7, #nzcV"
"lsl w0, w27, #24",
"cmp w0, w20, lsl #24",
"cfinv"
]
},
"add al, -1": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"add w26, w20, #0xff (255)",
"mov w20, #0xff",
"mov x21, x4",
"add w26, w21, #0xff (255)",
"mov x4, x21",
"bfxil x4, x26, #0, #8",
"eor w27, w20, #0xff",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"bic w20, w20, w26",
"rmif x20, #7, #nzcV"
"eor w27, w21, #0xff",
"lsl w0, w21, #24",
"cmn w0, w20, lsl #24"
]
},
"or al, -1": {
Expand Down Expand Up @@ -211,17 +212,18 @@
]
},
"sub al, -1": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 9,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"sub w26, w20, #0xff (255)",
"mov w20, #0xff",
"mov x21, x4",
"sub w26, w21, #0xff (255)",
"mov x4, x21",
"bfxil x4, x26, #0, #8",
"eor w27, w20, #0xff",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"bic w20, w26, w20",
"rmif x20, #7, #nzcV"
"eor w27, w21, #0xff",
"lsl w0, w21, #24",
"cmp w0, w20, lsl #24",
"cfinv"
]
},
"xor al, -1": {
Expand All @@ -234,29 +236,28 @@
]
},
"cmp al, -1": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x80 /7",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"sub w26, w20, #0xff (255)",
"eor w27, w20, #0xff",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"bic w20, w26, w20",
"rmif x20, #7, #nzcV"
"mov w20, #0xff",
"sub w26, w4, #0xff (255)",
"eor w27, w4, #0xff",
"lsl w0, w4, #24",
"cmp w0, w20, lsl #24",
"cfinv"
]
},
"add ax, 256": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"uxth w27, w4",
"mov w20, #0x100",
"mov x27, x4",
"add w26, w27, #0x100 (256)",
"mov x4, x27",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV"
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16"
]
},
"add eax, 256": {
Expand Down Expand Up @@ -430,17 +431,16 @@
]
},
"add ax, -256": {
"ExpectedInstructionCount": 8,
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xff00",
"uxth w27, w4",
"mov x27, x4",
"add w26, w27, w20",
"mov x4, x27",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"bic w20, w27, w26",
"rmif x20, #15, #nzcV"
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16"
]
},
"add eax, -256": {
Expand Down Expand Up @@ -623,13 +623,13 @@
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"uxth w27, w4",
"mov w20, #0x1",
"mov x27, x4",
"add w26, w27, #0x1 (1)",
"mov x4, x27",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV"
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16"
]
},
"add eax, 1": {
Expand Down Expand Up @@ -803,18 +803,17 @@
]
},
"add ax, -1": {
"ExpectedInstructionCount": 9,
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"uxth w21, w4",
"mov x21, x4",
"add w26, w21, w20",
"mov x4, x21",
"bfxil x4, x26, #0, #16",
"eor w27, w21, #0xffff",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"bic w20, w21, w26",
"rmif x20, #15, #nzcV"
"lsl w0, w21, #16",
"cmn w0, w20, lsl #16"
]
},
"add eax, -1": {
Expand Down Expand Up @@ -2236,16 +2235,14 @@
]
},
"neg bl": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
"uxtb w27, w7",
"neg w26, w27",
"bfxil x7, x26, #0, #8",
"cmn wzr, w26, lsl #24",
"rmif x26, #7, #nzCv",
"and w20, w26, w27",
"rmif x20, #7, #nzcV"
"cmp wzr, w27, lsl #24",
"cfinv"
]
},
"mul bl": {
Expand Down Expand Up @@ -2356,16 +2353,14 @@
]
},
"neg bx": {
"ExpectedInstructionCount": 7,
"ExpectedInstructionCount": 5,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"uxth w27, w7",
"neg w26, w27",
"bfxil x7, x26, #0, #16",
"cmn wzr, w26, lsl #16",
"rmif x26, #15, #nzCv",
"and w20, w26, w27",
"rmif x20, #15, #nzcV"
"cmp wzr, w27, lsl #16",
"cfinv"
]
},
"neg ebx": {
Expand Down Expand Up @@ -2492,42 +2487,42 @@
"ExpectedInstructionCount": 8,
"Comment": "GROUP3 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"uxtb w27, w4",
"add w26, w27, #0x1 (1)",
"bfxil x4, x26, #0, #8",
"cset w20, hs",
"cmn wzr, w26, lsl #24",
"bic w21, w26, w27",
"rmif x21, #7, #nzcV",
"rmif x20, #63, #nzCv"
"cset w21, hs",
"lsl w0, w27, #24",
"cmn w0, w20, lsl #24",
"rmif x21, #63, #nzCv"
]
},
"dec al": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP3 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"uxtb w27, w4",
"sub w26, w27, #0x1 (1)",
"bfxil x4, x26, #0, #8",
"cset w20, hs",
"cmn wzr, w26, lsl #24",
"bic w21, w27, w26",
"rmif x21, #7, #nzcV",
"rmif x20, #63, #nzCv"
"cset w21, hs",
"lsl w0, w27, #24",
"cmp w0, w20, lsl #24",
"rmif x21, #63, #nzCv"
]
},
"inc ax": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"uxth w27, w4",
"add w26, w27, #0x1 (1)",
"bfxil x4, x26, #0, #16",
"cset w20, hs",
"cmn wzr, w26, lsl #16",
"bic w21, w26, w27",
"rmif x21, #15, #nzcV",
"rmif x20, #63, #nzCv"
"cset w21, hs",
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16",
"rmif x21, #63, #nzCv"
]
},
"inc eax": {
Expand Down Expand Up @@ -2558,14 +2553,14 @@
"ExpectedInstructionCount": 8,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"uxth w27, w4",
"sub w26, w27, #0x1 (1)",
"bfxil x4, x26, #0, #16",
"cset w20, hs",
"cmn wzr, w26, lsl #16",
"bic w21, w27, w26",
"rmif x21, #15, #nzcV",
"rmif x20, #63, #nzCv"
"cset w21, hs",
"lsl w0, w27, #16",
"cmp w0, w20, lsl #16",
"rmif x21, #63, #nzCv"
]
},
"dec eax": {
Expand Down
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