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Fix FXTRACT for 0.0 and -0.0 #4093

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merged 4 commits into from
Oct 17, 2024
Merged

Fix FXTRACT for 0.0 and -0.0 #4093

merged 4 commits into from
Oct 17, 2024

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pmatos
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@pmatos pmatos commented Sep 30, 2024

Fixes fxtract by returning the correct values for 0.0 and -0.0. We moved the split of fxtract into _sig and _exp, to the opcode dispatcher, to ease some comparisons.

Also removed the IR node F80XTRACTStack which is not needed anymore.

Depends on landing #4092 (commit d62dd50 included here but to be merged separately)

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pmatos commented Sep 30, 2024

For context the spec mentions that for fscale:

The FSCALE instruction can also be used to reverse the action of the FXTRACT instruction, as shown in the following example:

FXTRACT;
FSCALE;
FSTP ST(1);

When testing this, through FScaleFXtract.asm unit test, I noticed that for 0.0 and -0.0, fxtract was generating incorrect values. I fixed these there.

@pmatos pmatos force-pushed the FXtractFix branch 6 times, most recently from 96fe7af to 6fe0e35 Compare October 2, 2024 15:44
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pmatos commented Oct 2, 2024

All good here now - instcounci failure coming from #4092 that needs to land before this one.

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pmatos commented Oct 7, 2024

pinging here for review!
One thing I would like another pair of eyes on is the IR definition of NZCVSelectV. Do we actually need to specify a ResultSize? Can't we just say that the ResultSize is the same size as the TrueVal (or FalseVal). Also maybe we need to validate that these have the same size?

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Seems reasonable to me, but I'll leave it to Alyssa for the IR change.

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pmatos commented Oct 15, 2024

ping @alyssarosenzweig

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instead of And+SubNZCV, just use TestNZ to save an instruction

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CondClassType {.Val = FEXCore::IR::COND_EQ} can maybe just be {COND_EQ}

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alyssarosenzweig commented Oct 15, 2024

+  Ref ExpNZ = _And(OpSize::i64Bit, Gpr, _Constant(0x7ff0000000000000LL));
+  ExpNZ = _Lshr(OpSize::i64Bit, ExpNZ, _Constant(52));

can you combine these two into a _Bfe instruction? (start=52, count=11 or something)

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+  Ref SigNZ = _And(OpSize::i64Bit, Gpr, _Constant(0x800fffffffffffffLL));
+  SigNZ = _Or(OpSize::i64Bit, SigNZ, _Constant(0x3ff0000000000000LL));

reexpress as x |( ~(1 << 63)) followed by x & ~(1 << 63). This lets you use constants that will inline, whereas these ones don't, thereby saving a few moves

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0x800f'ffff'ffff'ffff and 0x3ff0'0000'0000'0000 do successfully inline for logical op instructions. You can see it in the InstCountCI output.

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0x800f'ffff'ffff'ffff and 0x3ff0'0000'0000'0000 do successfully inline for logical op instructions. You can see it in the InstCountCI output.

Oops, right. disregard that part!

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as commented

Behaves like NZCVSelect for FPRs.
Fixes fxtract by returning the correct values for 0.0 and -0.0. We moved the split of fxtract into _sig and _exp, to the opcode dispatcher, to ease some comparisons.

Also removed the IR node F80XTRACTStack which is not needed anymore.
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pmatos commented Oct 17, 2024

as commented

Thanks for the comments - I think I have addressed them now.

@Sonicadvance1 Sonicadvance1 merged commit a421ff1 into FEX-Emu:main Oct 17, 2024
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5 participants