sun8i V3s usb ethernet #1
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Allwinner SoCs after H3 (e.g. A64, H5, R40, V3s) uses a H3-like DesignWare DRAM controller, which do not have official free DRAM initialization code, but can use modified dram_sun8i_h3.c. Add a invisible option for easier DRAM initialization code reuse. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
According to Jens disabling the on-die-termination should set bit 5, not bit 1 in the respective register. Fix this. Reported-by: Jens Kuske <jenskuske@gmail.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
H3-like DRAM controller needs some special code to operate a DDR2 DRAM chip. Add the logic to probe such a chip. As there's no commercial boards available now with H3 and DDR2 DRAM, the patch is developed and tested on a V3s chip, which has in-package DDR2 DRAM. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Currently a working SPL for V3s can be built now. The U-Boot main binary still cannot work. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
As we have now V3s support in board code, the V3s DTSI file should also be added. Add also some CCU include headers to satisfy the DTSI file. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Lichee Pi Zero is a development board with a V3s SoC. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
V3s devices won't have enough memory to load U-Boot binary at 0x4a000000, and they do not have enough memory to reserve 64MiB for malloc() (it has only 64MiB at all!) Change the DRAM mapping for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
USB OTG on V3s SoC seems to need the USB OTG clock gate to be passed and the reset to be deasserted before boot, otherwise it won't work in Linux. Add this quirk. Also add a generic quirk framework in sunxi's clock initialization code. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
This is needed for HDMI support, which will be added later. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> [Icenowy: renamed back lcd0_ch0_clk_cfg, add PLL3 for DE2 on V3s, and add CONFIG_SUNXI_DE2] Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
V3s SoC features a DE2 composer. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
DE2 do not have dedicated BE or FE. Remove the "_be" suffix in the pipeline string of DE2. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
The cache of Cortex-A7 is only enabled if the SMP bit is set, but the SMP bit of V3s is wrongly left unset, because I thought that it's not SMP-capable. Fix this. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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Add usb ethernet support for v3s camdroid board |
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Add usb ethernet support for v3s camdroid board