Skip to content

Commit

Permalink
[RISCV] Make Zcmt imply Zicsr. (llvm#75464)
Browse files Browse the repository at this point in the history
This patch fixes build attributes w/r to Zcmt extension dependency on
Zicsr.
  • Loading branch information
yroux authored Dec 20, 2023
1 parent a756dc4 commit 06d10d4
Show file tree
Hide file tree
Showing 3 changed files with 6 additions and 4 deletions.
2 changes: 1 addition & 1 deletion llvm/lib/Support/RISCVISAInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1007,7 +1007,7 @@ static const char *ImpliedExtsZcd[] = {"d", "zca"};
static const char *ImpliedExtsZce[] = {"zcb", "zcmp", "zcmt"};
static const char *ImpliedExtsZcf[] = {"f", "zca"};
static const char *ImpliedExtsZcmp[] = {"zca"};
static const char *ImpliedExtsZcmt[] = {"zca"};
static const char *ImpliedExtsZcmt[] = {"zca", "zicsr"};
static const char *ImpliedExtsZdinx[] = {"zfinx"};
static const char *ImpliedExtsZfa[] = {"f"};
static const char *ImpliedExtsZfbfmin[] = {"f"};
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/MC/RISCV/attribute-arch.s
Original file line number Diff line number Diff line change
Expand Up @@ -244,7 +244,7 @@
# CHECK: attribute 5, "rv32i2p1_zca1p0_zcmp1p0"

.attribute arch, "rv32izcmt1p0"
# CHECK: attribute 5, "rv32i2p1_zca1p0_zcmt1p0"
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zca1p0_zcmt1p0"

.attribute arch, "rv64i_xsfvcp"
# CHECK: attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0"
Expand Down
6 changes: 4 additions & 2 deletions llvm/unittests/Support/RISCVISAInfoTest.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -519,8 +519,9 @@ TEST(ParseArchString, ZceImplication) {
ASSERT_THAT_EXPECTED(MaybeRV32IZce, Succeeded());
RISCVISAInfo::OrderedExtensionMap ExtsRV32IZce =
(*MaybeRV32IZce)->getExtensions();
EXPECT_EQ(ExtsRV32IZce.size(), 6UL);
EXPECT_EQ(ExtsRV32IZce.size(), 7UL);
EXPECT_EQ(ExtsRV32IZce.count("i"), 1U);
EXPECT_EQ(ExtsRV32IZce.count("zicsr"), 1U);
EXPECT_EQ(ExtsRV32IZce.count("zca"), 1U);
EXPECT_EQ(ExtsRV32IZce.count("zcb"), 1U);
EXPECT_EQ(ExtsRV32IZce.count("zce"), 1U);
Expand Down Expand Up @@ -562,8 +563,9 @@ TEST(ParseArchString, ZceImplication) {
ASSERT_THAT_EXPECTED(MaybeRV64IZce, Succeeded());
RISCVISAInfo::OrderedExtensionMap ExtsRV64IZce =
(*MaybeRV64IZce)->getExtensions();
EXPECT_EQ(ExtsRV64IZce.size(), 6UL);
EXPECT_EQ(ExtsRV64IZce.size(), 7UL);
EXPECT_EQ(ExtsRV64IZce.count("i"), 1U);
EXPECT_EQ(ExtsRV64IZce.count("zicsr"), 1U);
EXPECT_EQ(ExtsRV64IZce.count("zca"), 1U);
EXPECT_EQ(ExtsRV64IZce.count("zcb"), 1U);
EXPECT_EQ(ExtsRV64IZce.count("zce"), 1U);
Expand Down

0 comments on commit 06d10d4

Please sign in to comment.