-
Notifications
You must be signed in to change notification settings - Fork 52
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
tune heuristics for inner outer scheduler after cached inputs are moved to smem #3223
Draft
liqiangxl
wants to merge
16
commits into
llu/inner_outer_smem_moveall
Choose a base branch
from
llullu/move_all_pow2_heuristics
base: llu/inner_outer_smem_moveall
Could not load branches
Branch not found: {{ refName }}
Loading
Could not load tags
Nothing to show
Loading
Are you sure you want to change the base?
Some commits from the old base branch may be removed from the timeline,
and old review comments may become outdated.
Draft
tune heuristics for inner outer scheduler after cached inputs are moved to smem #3223
liqiangxl
wants to merge
16
commits into
llu/inner_outer_smem_moveall
from
llullu/move_all_pow2_heuristics
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
!build |
!build --pybench |
!build --pybench |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Issue:
After all inner persistent buffers are moved to shared memory, the register buffer size is 4 and 8 bytes per element for RMS norm backward and layer norm backward. Current heuristics uses the largest possible batch size and leads to performance regressions. For exammpe, in RMS norm at hidden size 20K, will use 20 bathes with 128 threads. The batch size is too large and caused register spills, should consider increase threads per block to reduce batch size.
Fix:
(1) Max threads per block is increased from 256 to 512 due to reduced register pressures.
(2) Generate candidate heuristics using different threads per block and sort these heuristics based on register usage and occupancy.
Generate candidate heuristic:
Sort candidates based on:
Results:
Hopper:
(1) layer norm and rms nomr bwd, fp16
(2) layer norm and rms nomr bwd, fp32
Amper: see dashboard