docs(01_Instruction_Cache.md): Added I/O Lines for RAM Access

Documentation/04_Connecting_Module_Docs/01_Instruction_Cache.md

@@ -1,7 +1,7 @@
 THIS OUTLINE IS INCOMPLETE
 
 # Instruction Cache #
-(Verilog module known as Conn_Instruction_Cache)
+(Verilog module known as Con_Instruction_Cache)
 
 ## Contents
 * [Inputs](#inputs)
@@ -17,11 +17,18 @@ THIS OUTLINE IS INCOMPLETE
 |```cache_clk```|1-bit|
 |```rstn```|1-bit|
 |```pc```|32-bit|
+|```mem_response_data```|32-bit|
+|```mem_busy```|1-bit|
 
 ## Outputs
 |Name|Bits wide|
 |:---|:---:|
 |```ins```|32-bit|
+|```wEn```|1-bit|
+|```rEn```|1-bit|
+|```isBurst```|1-bit|
+|```mem_address```|32-bit|
+|```mem_write_data```|32-bit|
 
 ## Modules