Merge branch 'NYU-Processor-Design:main' into main

.github/workflows/main.yaml

@@ -13,7 +13,7 @@ jobs:
           pacman --noconfirm -S cmake ninja git curl zip unzip tar verilator
 
       - name: Checkout
-        uses: actions/checkout@v3
+        uses: actions/checkout@v4
 
       - name: Configure
         run: cmake . -G Ninja -DNYU_BUILD_TESTS=ON
@@ -24,10 +24,12 @@ jobs:
       - name: Test & Generate Coverage
         run: |
           ctest -C Release --output-on-failure
+          sed -i -e '/\/share\//d' -e '/\/dv\//d' dv/*.dat
           verilator_coverage -write-info coverage.txt dv/*.dat
 
       - name: Upload Coverage
-        uses: codecov/codecov-action@v3
+        uses: codecov/codecov-action@v4
         with:
+          token: ${{ secrets.CODECOV_TOKEN }}
           files: ./coverage.txt
           fail_ci_if_error: true

CMakeLists.txt

@@ -1,26 +1,6 @@
 cmake_minimum_required(VERSION 3.27)
 
-if(NOT SKIP_VCPKG AND NOT DEFINED CMAKE_TOOLCHAIN_FILE)
-  include(FetchContent)
-  FetchContent_Declare(
-    vcpkg
-    GIT_REPOSITORY https://github.com/microsoft/vcpkg.git
-    GIT_TAG master
-    GIT_SHALLOW TRUE
-  )
-  FetchContent_MakeAvailable(vcpkg)
-  set(CMAKE_TOOLCHAIN_FILE
-    ${vcpkg_SOURCE_DIR}/scripts/buildsystems/vcpkg.cmake
-    CACHE FILEPATH "Vcpkg toolchain file"
-  )
-  set(VCPKG_ROOT_DIR ${vcpkg_SOURCE_DIR} CACHE PATH "Vcpkg Root Directory")
-endif()
-
-if(DEFINED VCPKG_ROOT_DIR)
-  add_custom_target(UpdateVcpkgBaseline
-    ${VCPKG_ROOT_DIR}/vcpkg x-update-baseline
-  )
-endif()
+include(cmake/BootstrapVcpkg.cmake)
 
 project(nyu-core VERSION 1.0.0)
 

Documentation/01_Module_Docs/00_CPU_general_purpose_registers.md

@@ -15,7 +15,7 @@ Note: Register 0 always returns 0 while registers 1-31 are general-purpose 32-bi
 |Name|Bits wide|
 |:---|:---:|
 |```clk```|1-bit|
-|```rstn```|1-bit|
+|```rstn_h```|1-bit|
 |```rs1n```|5-bits|
 |```rs2n```|5-bits|
 |```rdn```|5-bits|

Documentation/01_Module_Docs/01_IF_ID_latch.md

@@ -40,10 +40,10 @@
     |```immode```|```imm```|
     |:---:|---|
     |```immode == 0```|```imm = 32’b0```|
-    |```immode == 1```|```imm = {20{ins[31]}}, ins[31:20]}```|
-    |```immode == 2```|```imm = {20{ins[31]}}, ins[31: 25], ins[11:7]}```|
-    |```immode == 3```|```imm = {20{ins[31]}}, ins[7], ins[30:25], ins[11:8], 0}```|
-    |```immode == 4```|```imm = {ins[31:12], 12b’0}```|
-    |```immode == 5```|```imm = {11’b0, ins[31], ins[19:12], ins[20], ins[30:21], 0}```|
+    |```immode == 1```|```imm = {{20{ins[31]}}, ins[31:20]}```|
+    |```immode == 2```|```imm = {{20{ins[31]}}, ins[31:25], ins[11:7]}```|
+    |```immode == 3```|```imm = {{20{ins[31]}}, ins[7], ins[30:25], ins[11:8], 1'b0}```|
+    |```immode == 4```|```imm = {ins[31:12], 12’b0}```|
+    |```immode == 5```|```imm = {11’b0, ins[31], ins[19:12], ins[20], ins[30:21], 1'b0}```|
 ### Asynchronous active low reset
   - Register values reset to 0

Documentation/01_Module_Docs/05_General_Control_Module.md

@@ -87,7 +87,7 @@
     |```EX_ins[6:0]```|```alu_mode```|```branch_cond```|
     |---|---|---|
     |```EX_ins[6:0]``` == R|```alu_mode``` = ```EX_ins[31:25]``` + ```EX_ins[14:12]```|```branch_cond``` = 0|
-    |```EX_ins[6:0]``` == I1|```alu_mode``` = ```EX_ins[31:25]``` + ```EX_ins[14:12]``` if ```EX_ins[14:12]``` == 0x5, ```alu_mode``` = ```EX_ins[14:12]```|```branch_cond``` = 0 otherwise|
+    |```EX_ins[6:0]``` == I1|```alu_mode``` = ```EX_ins[31:25]``` + ```EX_ins[14:12]``` if ```EX_ins[14:12]``` == 0x5, otherwise ```alu_mode``` = ```EX_ins[14:12]```|```branch_cond``` = 0|
     |```EX_ins[6:0]``` == I2|```alu_mode``` = 0|```branch_cond``` = 0|
     |```EX_ins[6:0]``` == I3|```alu_mode``` = 0|```branch_cond``` = 3|
     |```EX_ins[6:0]``` == S|```alu_mode``` = 0|```branch_cond``` = 0|
@@ -125,13 +125,13 @@
 - If (```ins[6:0]``` == I3, B, J) and (```hazard``` == 0)
      - ```hazard``` = 1
 - Else if ```ins[6:0]``` == R, I1, I2, I3, S, B, U, J
-     - If (```ID_ins[6:0]``` == R, I1, I2, I3, U, J) and (```ID_ins[11:7]``` == ```ins[11:7]```) and (```ID_ins[11:7]``` != 0)
+     - If (```ID_ins[6:0]``` == R, I1, I2, I3, U, J) and ((```ID_ins[11:7]``` == ```ins[11:7]```) or (```ID_ins[11:7]``` == ```ins[24:20]```) or (```ID_ins[11:7]``` == ```ins[19:15]```))and (```ID_ins[11:7]``` != 0)
           - ```hazard``` = 1
-     - If (```EX_ins[6:0]``` == R, I1, I2, I3, U, J) and (```EX_ins[11:7]``` == ```ins[11:7]```) and (```EX_ins[11:7]``` != 0)
+     - If (```EX_ins[6:0]``` == R, I1, I2, I3, U, J) and ((```EX_ins[11:7]``` == ```ins[11:7]```) or (```EX_ins[11:7]``` == ```ins[24:20]```) or (```EX_ins[11:7]``` == ```ins[19:15]```))and (```EX_ins[11:7]``` != 0)
           - ```hazard``` = 1
-     - If (```MEM_ins[6:0]``` == R, I1, I2, I3, U, J) and (```MEM_ins[11:7]``` == ```ins[11:7]```) and (```MEM_ins[11:7]``` != 0)
+     - If (```MEM_ins[6:0]``` == R, I1, I2, I3, U, J) and ((```MEM_ins[11:7]``` == ```ins[11:7]```) or (```MEM_ins[11:7]``` == ```ins[24:20]```) or (```MEM_ins[11:7]``` == ```ins[19:15]```))and (```MEM_ins[11:7]``` != 0)
           - ```hazard``` = 1
-     - If (```WB_ins[6:0]``` == R, I1, I2, I3, U, J) and (```WB_ins[11:7]``` == ```ins[11:7]```) and and (```WB_ins[11:7]``` != 0)
+     - If (```WB_ins[6:0]``` == R, I1, I2, I3, U, J) and ((```WB_ins[11:7]``` == ```ins[11:7]```) or (```WB_ins[11:7]``` == ```ins[24:20]```) or (```WB_ins[11:7]``` == ```ins[19:15]```))and (```WB_ins[11:7]``` != 0)
           - ```hazard``` = 1
 - Else
      - ```hazard``` = 0

Documentation/01_Module_Docs/16_Branch_Predictor.md

@@ -43,7 +43,7 @@
     |---|---|---|
     |^```branch_cond``` == 0|```curr_pred``` = ```curr_pred```|```incorrect_pred``` = ```incorrect_pred```|
     |(^```branch_cond``` == 1) & (```act_taken```^```pred_taken``` == 0)|```curr_pred``` = ```curr_pred```|```incorrect_pred``` = 0|
-     |(^```branch_cond``` == 1) & (```act_taken```^```pred_taken``` == 1) & (```incorrect_pred``` == 1|```curr_pred``` = ~```curr_pred```|```incorrect_pred``` = 1|
+     |(^```branch_cond``` == 1) & (```act_taken```^```pred_taken``` == 1) & (```incorrect_pred``` == 1)|```curr_pred``` = ~```curr_pred```|```incorrect_pred``` = 1|
     |(^```branch_cond``` == 1) & (```act_taken```^```pred_taken``` == 1) & (```incorrect_pred``` == 0)|```curr_pred``` = ```curr_pred```|```incorrect_pred``` = 1|
 
 ### Asynchronous active low reset on rstn_h

Documentation/04_Connecting_Module_Docs/00_Top_Level.md

@@ -88,6 +88,7 @@ THIS OUTLINE IS INCOMPLETE
 |Name|Bits wide|
 |:---:|:---:|
 |```rstn```|1-bit|
+|```rstn_h```|1-bit|
 |```pc_en```|1-bit|
 |```npc```|32-bit|
 
@@ -113,6 +114,7 @@ THIS OUTLINE IS INCOMPLETE
 |Name|Bits wide|
 |:---:|:---:|
 |```rstn```|1-bit|
+|```rstn_h```|1-bit|
 |```immode```|3-bit|
 |```ins```|32-bit|
 |```pc_in```|32-bit|

Documentation/04_Connecting_Module_Docs/03_IF_Connection_Module.md

@@ -17,6 +17,7 @@ THIS OUTLINE IS INCOMPLETE
 |```clk```|1-bit|
 |```cache_clk```|1-bit|
 |```rstn```|1-bit|
+|```rstn_h```|1-bit|
 |```pc_en```|1-bit|
 |```npc```|32-bit|
 
@@ -60,7 +61,7 @@ THIS OUTLINE IS INCOMPLETE
 |Name|Bits wide|
 |:---:|:---:|
 |```cache_clk```|1-bit|
-|```rstn```|1-bit|
+|```rstn_h```|1-bit|
 |```mem_response_data```|32-bit|
 |```mem_busy```|1-bit|
 

Documentation/04_Connecting_Module_Docs/04_ID_Connection_Module.md

@@ -16,6 +16,7 @@
 |```clk```|1-bit|
 |```cache_clk```|1-bit|
 |```rstn```|1-bit|
+|```rstn_h```|1-bit|
 |```immode```|3-bit|
 |```ins```|32-bit|
 |```pc_in```|32-bit|
@@ -76,7 +77,7 @@
 |Name|Bits wide|
 |:---:|:---:|
 |```cache_clk```|1-bit|
-|```rstn```|1-bit|
+|```rstn_h```|1-bit|
 |```wbe```|1-bit|
 |```rdn_in```|5-bit|
 |```rdd```|32-bit|

ReadMe.md

@@ -3,7 +3,7 @@
 [![github](https://github.com/NYU-Processor-Design/nyu-core/actions/workflows/main.yaml/badge.svg)](https://github.com/NYU-Processor-Design/nyu-core/actions) 
 [![codecov](https://codecov.io/gh/NYU-Processor-Design/nyu-core/branch/main/graph/badge.svg?token=McspW0gLf4)](https://codecov.io/gh/NYU-Processor-Design/nyu-core) 
 
-The NYU ProcDesign Core will be a RISCV-32I compatible core with a 5 stage pipeline.
+The NYU ProcDesign Core will be a RISCV-32I compatible core with a 5-stage pipeline.
 
 The repo contains the modules and test for components that make up the core design.
 
@@ -48,7 +48,7 @@ Control Modules:
 - [Processor State Module](/Documentation/01_Module_Docs/08_Processor_State.md)
 - [Pipeline Reset Module](/Documentation/01_Module_Docs/05_General_Control_Module.md)
 
-## Cache
+## Caches
 
 Cache Modules:
 - [Instruction Cache Manager](/Documentation/01_Module_Docs/13_Instruction_Cache_Manager.md)
@@ -58,7 +58,7 @@ Cache Modules:
 
 ## Current Draft of CPU Diagram
 
-![cpu](https://github.com/NYU-Processor-Design/nyu-core/assets/114675487/c6bc4d3d-5b68-4946-b2b9-0785326a6d8d)
+![cpu](https://github.com/NYU-Processor-Design/nyu-core/assets/114675487/dae24858-cc97-4ac2-8df8-7af0b9853e57)
 
 ## Further Reading
 

cmake/BootstrapVcpkg.cmake

@@ -0,0 +1,45 @@
+if(NOT SKIP_VCPKG AND NOT DEFINED CMAKE_TOOLCHAIN_FILE)
+  include(FetchContent)
+
+  if(WIN32)
+    set(VCPKG vcpkg.exe)
+  elseif(LINUX)
+    if(EXISTS "/etc/alpine-release")
+      set(VCPKG vcpkg-musl)
+    else()
+      set(VCPKG vcpkg-glibc)
+    endif()
+  elseif(APPLE)
+    set(VCPKG vcpkg-macos)
+  else()
+    message(FATAL_ERROR "Cannot bootstrap vcpkg: Unsupported platform")
+  endif()
+
+  FetchContent_Declare(vcpkg
+    URL https://github.com/microsoft/vcpkg-tool/releases/latest/download/${VCPKG}
+    DOWNLOAD_NO_EXTRACT TRUE
+  )
+
+  FetchContent_MakeAvailable(vcpkg)
+  set(VCPKG ${vcpkg_SOURCE_DIR}/${VCPKG})
+
+  file(CHMOD ${VCPKG} PERMISSIONS OWNER_READ OWNER_WRITE OWNER_EXECUTE)
+  set(ENV{VCPKG_ROOT} ${vcpkg_SOURCE_DIR})
+  execute_process(COMMAND ${VCPKG} bootstrap-standalone)
+
+  if(NOT WIN32)
+    file(RENAME ${VCPKG} ${vcpkg_SOURCE_DIR}/vcpkg)
+  endif()
+
+  set(CMAKE_TOOLCHAIN_FILE
+    ${vcpkg_SOURCE_DIR}/scripts/buildsystems/vcpkg.cmake
+    CACHE FILEPATH "Vcpkg toolchain file"
+  )
+  set(VCPKG_ROOT_DIR ${vcpkg_SOURCE_DIR} CACHE PATH "Vcpkg Root Directory")
+endif()
+
+if(DEFINED VCPKG_ROOT_DIR)
+  add_custom_target(UpdateVcpkgBaseline
+    ${VCPKG_ROOT_DIR}/vcpkg x-update-baseline
+  )
+endif()

dv/CMakeLists.txt

@@ -3,17 +3,62 @@ find_package(nyu-util REQUIRED CONFIG)
 
 add_executable(tests)
 target_sources(tests PRIVATE
+  alu.cpp
 
+  branch_addr_calc.cpp
+  branch_eval.cpp
+  branch_manager.cpp
+  branch_predictor.cpp
 
-con_ex.cpp alu.cpp con_branch_cont.cpp branch_eval.cpp pc.cpp ifid.cpp memwb.cpp gpr.cpp exmem.cpp branch_addr_calc.cpp idex.cpp branch_predictor.cpp pipeline_reset.cpp branch_manager.cpp data_cache_manager.cpp
+  con_branch_cont.cpp
+  con_ex.cpp
+  con_id.cpp
 
+  data_cache_manager.cpp
+  exmem.cpp
+
+  gpr.cpp
+  idex.cpp
+  ifid.cpp
+
+  # Failing
+  # l1_data_cache.cpp
+
+  memwb.cpp
+  pc.cpp
+  pipeline_reset.cpp
 )
+
 nyu_link_sv(tests PRIVATE core)
 nyu_target_verilate(tests
-  TOP_MODULES Con_EX Alu Con_Branch_Cont Branch_Eval PC IFID MEMWB GPR EXMEM Branch_Addr_Calc IDEX Branch_Predictor Pipeline_Reset Branch_Manager Data_Cache_Manager
+  ARGS COVERAGE TRACE_FST
+  TOP_MODULES 
+  Alu
+
+  Branch_Addr_Calc
+  Branch_Eval
+  Branch_Manager
+  Branch_Predictor
 
-  ARGS COVERAGE
+  Con_Branch_Cont 
+  Con_EX
+  Con_ID
+
+  Data_Cache_Manager
+  EXMEM
+
+  GPR
+  IDEX
+  IFID
+
+  # Failing
+  # L1_Data_Cache
+
+  MEMWB
+  PC  
+  Pipeline_Reset      
 )
+
 target_link_libraries(tests PRIVATE Catch2::Catch2WithMain nyu::covrecorder)
 target_compile_features(tests PRIVATE cxx_std_23)
 

dv/branch_addr_calc.cpp

@@ -26,9 +26,9 @@ static void eval(bool mode, bool taken, std::uint32_t imm, std::uint32_t rs1d, s
 }
 
 static void test(bool mode, bool taken) {
-    for(std::uint32_t imm {0}; imm < 128; ++imm)
-        for(std::uint32_t rs1d {0}; rs1d < 128; ++rs1d)
-            for(std::uint32_t pc_in {0}; pc_in < 128; ++pc_in)
+    for(std::uint32_t imm {0}; imm < 32; ++imm)
+        for(std::uint32_t rs1d {0}; rs1d < 32; ++rs1d)
+            for(std::uint32_t pc_in {0}; pc_in < 32; ++pc_in)
                 eval(mode, taken, imm, rs1d, pc_in);
 
     for(std::uint32_t imm {1}; imm; imm <<= 1)
@@ -38,18 +38,18 @@ static void test(bool mode, bool taken) {
 }
 
 
-TEST_CASE("PC No Branch") {  //Case when branch_addr = pc + imm, but branch is not taken (addr mode 0, taken 0)
+TEST_CASE("Branch Address Calculator, PC No Branch") {  //Case when branch_addr = pc + imm, but branch is not taken (addr mode 0, taken 0)
    test(0, 0);
 }
 
-TEST_CASE("PC Branch") { //Case when branch_addr = pc + imm, and branch is taken (addr mode 0, taken 1)
+TEST_CASE("Branch Address Calculator, PC Branch") { //Case when branch_addr = pc + imm, and branch is taken (addr mode 0, taken 1)
     test(0, 1);
 }
 
-TEST_CASE("RS1D No Branch") { //Case when branch_addr = imm + rs1d, but branch is not taken (addr mode 1, taken 0)
+TEST_CASE("Branch Address Calculator, RS1D No Branch") { //Case when branch_addr = imm + rs1d, but branch is not taken (addr mode 1, taken 0)
     test(1, 0);
 }
 
-TEST_CASE("RS1D Branch") { //Case when branch_addr = rs1d, and branch is taken (addr mode 1, taken 1)
+TEST_CASE("Branch Address Calculator, RS1D Branch") { //Case when branch_addr = rs1d, and branch is taken (addr mode 1, taken 1)
    test(1, 1);
 }

dv/branch_eval.cpp

@@ -34,25 +34,25 @@ static void eval(uint8_t cond, std::uint32_t alu_out) {
 
 
 static void test(std::uint8_t cond) {
-    for(std::uint32_t alu_out {0}; alu_out < 2048; ++alu_out)
+    for(std::uint32_t alu_out {0}; alu_out < 512; ++alu_out)
         eval(cond, alu_out);
 
     for(std::uint32_t alu_out {1}; alu_out; alu_out <<= 1)
         eval(cond, alu_out);
 }
 
-TEST_CASE("Never Branch") {  //Case when non branching instruction
+TEST_CASE("Branch Evaluator, Never Branch") {  //Case when non branching instruction
     test(0);
 }
 
-TEST_CASE("Branch if ALU_OUT is Non-Zero") { //Case when branch condition is < or !=
+TEST_CASE("Branch Evaluator, Branch if ALU_OUT is Non-Zero") { //Case when branch condition is < or !=
     test(1);
 }
 
-TEST_CASE("Branch if ALU_OUT is Zero") { //Case when branch condition is >= or =
+TEST_CASE("Branch Evaluator, Branch if ALU_OUT is Zero") { //Case when branch condition is >= or =
     test(2);
 }
 
-TEST_CASE("Always Branch") { //Case when jump instruction
+TEST_CASE("Branch Evaluator, Always Branch") { //Case when jump instruction
    test(3);
 }

dv/branch_manager.cpp

@@ -53,8 +53,8 @@ static void test() {
     auto& bman {nyu::getDUT<VBranch_Manager>()};
 
     init(bman);
-    for(std::uint32_t pred_pc {0}; pred_pc < 128; ++pred_pc)
-        for(std::uint32_t pred_addr {0}; pred_addr < 128; ++pred_addr)
+    for(std::uint32_t pred_pc {0}; pred_pc < 32; ++pred_pc)
+        for(std::uint32_t pred_addr {0}; pred_addr < 32; ++pred_addr)
             for(int pred_taken {0}; pred_taken < 2; ++pred_taken)
                 for(int act_taken {0}; act_taken < 2; ++act_taken)
                     eval(bman, pred_taken, act_taken, pred_pc, pred_addr);

dv/branch_predictor.cpp

@@ -66,10 +66,10 @@ static void test(bool pred) {
             }
 }
 
-TEST_CASE("Non Prediction Instruction") { //branch_occr = 0 or 1
+TEST_CASE("Branch Predictor, Non Prediction Instruction") { //branch_occr = 0 or 1
     test(0);
 }
 
-TEST_CASE("Prediction Instruction") { //branch_occr = 2 or 3
+TEST_CASE("Branch Predictor, Prediction Instruction") { //branch_occr = 2 or 3
     test(1);
 }