plat-stm32mp1: upgrade to new interrupt framework

Moves plat-stm32mp1 to the new interrupt framework API functions.

Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>

core/arch/arm/plat-stm32mp1/plat_tzc400.c

@@ -71,6 +71,7 @@ static bool tzc_region_is_secure(unsigned int i, vaddr_t base, size_t size)
 
 static TEE_Result init_stm32mp1_tzc(void)
 {
+	TEE_Result res = TEE_ERROR_GENERIC;
 	void *base = phys_to_virt(TZC_BASE, MEM_AREA_IO_SEC, 1);
 	unsigned int region_index = 1;
 	const uint64_t dram_start = DDR_BASE;
@@ -108,8 +109,12 @@ static TEE_Result init_stm32mp1_tzc(void)
 			panic("Unexpected TZC area on non-secure region");
 	}
 
-	itr_add(&tzc_itr_handler);
-	itr_enable(tzc_itr_handler.it);
+	res = interrupt_add_handler_with_chip(interrupt_get_main_chip(),
+					      &tzc_itr_handler);
+	if (res)
+		panic();
+
+	interrupt_enable(tzc_itr_handler.chip, tzc_itr_handler.it);
 	tzc_set_action(TZC_ACTION_INT);
 
 	return TEE_SUCCESS;

core/arch/arm/plat-stm32mp1/pm/psci.c

@@ -132,6 +132,8 @@ static void raise_sgi0_as_secure(void)
 
 static void release_secondary_early_hpen(size_t __unused pos)
 {
+	struct itr_chip *itr_chip = interrupt_get_main_chip();
+
 	/* Need to send SIG#0 over Group0 after individual core 1 reset */
 	raise_sgi0_as_secure();
 	udelay(20);
@@ -142,7 +144,7 @@ static void release_secondary_early_hpen(size_t __unused pos)
 		   BOOT_API_A7_CORE1_MAGIC_NUMBER);
 
 	dsb_ishst();
-	itr_raise_sgi(GIC_SEC_SGI_0, TARGET_CPU1_GIC_MASK);
+	interrupt_raise_sgi(itr_chip, GIC_SEC_SGI_0, TARGET_CPU1_GIC_MASK);
 }
 
 /* Override default psci_cpu_on() with platform specific sequence */