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review4: Modify based on the feedback.
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Temporary use to code viewing and subsequent rebase to other commits

Signed-off-by: Xiaoxu Zeng <zengxiaoxu@huawei.com>
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@xiaoxuZeng
xiaoxuZeng committed May 20, 2023
1 parent 6077105 commit 0b07044
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Showing 8 changed files with 87 additions and 79 deletions.
5 changes: 5 additions & 0 deletions core/arch/arm/include/arm64.h
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Original file line number Diff line number Diff line change
Expand Up @@ -288,6 +288,11 @@ static inline __noprof void dsb_ishst(void)
asm volatile ("dsb ishst" : : : "memory");
}

static inline __noprof void dsb_osh(void)
{
asm volatile ("dsb osh" : : : "memory");
}

static inline __noprof void sev(void)
{
asm volatile ("sev" : : : "memory");
Expand Down
2 changes: 1 addition & 1 deletion core/drivers/crypto/caam/utils/utils_dmaobj.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -537,7 +537,7 @@ static TEE_Result check_buffer_boundary(struct caamdmaobj *obj,

for (idx = 0; idx < nb_pa_area && remlen; idx++) {
DMAOBJ_TRACE("Remaining length = %zu", remlen);
if (ADD_OVERFLOW(pabufs[idx].paddr, pabufs[idx].length,
if ((pabufs[idx].paddr, pabufs[idx].length,
&last_pa))
goto out;

Expand Down
90 changes: 45 additions & 45 deletions core/drivers/crypto/hisilicon/hisi_qm.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -138,7 +138,7 @@ static void qm_db(struct hisi_qm *qm, uint16_t qn, uint8_t cmd, uint16_t index,
io_write64(qm->io_base + QM_DOORBELL_SQ_CQ_BASE, doorbell);
}

static int32_t qm_wait_mb_ready(struct hisi_qm *qm)
static TEE_Result qm_wait_mb_ready(struct hisi_qm *qm)
{
uint32_t val = 0;

Expand All @@ -163,7 +163,7 @@ static void qm_mb_write(struct hisi_qm *qm, void *src)
dsb();
}

static int32_t qm_mb(struct hisi_qm *qm, uint8_t cmd, vaddr_t dma_addr,
static TEE_Result qm_mb(struct hisi_qm *qm, uint8_t cmd, vaddr_t dma_addr,
uint16_t qn, uint8_t op)
{
struct qm_mailbox mb = { };
Expand All @@ -176,14 +176,14 @@ static int32_t qm_mb(struct hisi_qm *qm, uint8_t cmd, vaddr_t dma_addr,

if (qm_wait_mb_ready(qm)) {
EMSG("QM mailbox is busy");
return -HISI_QM_DRVCRYPT_EBUSY;
return HISI_QM_DRVCRYPT_EBUSY;
}

qm_mb_write(qm, &mb);

if (qm_wait_mb_ready(qm)) {
EMSG("QM mailbox operation timeout");
return -HISI_QM_DRVCRYPT_EBUSY;
return HISI_QM_DRVCRYPT_EBUSY;
}

return HISI_QM_DRVCRYPT_NO_ERR;
Expand Down Expand Up @@ -215,11 +215,11 @@ static void qm_cfg_vft_data(struct hisi_qm *qm, uint8_t vft_type,
io_write32(qm->io_base + QM_VFT_CFG_DATA_H, data_h);
}

static int32_t qm_set_vft_common(struct hisi_qm *qm, uint8_t vft_type,
static TEE_Result qm_set_vft_common(struct hisi_qm *qm, uint8_t vft_type,
uint32_t function, uint32_t base, uint32_t num)
{
uint32_t val = 0;
int32_t ret = 0;
uint32_t ret = 0;

ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
val & QM_FVT_CFG_RDY_BIT, POLL_PERIOD,
Expand All @@ -241,15 +241,15 @@ static int32_t qm_set_vft_common(struct hisi_qm *qm, uint8_t vft_type,
POLL_TIMEOUT);
}

static int32_t qm_set_xqc_vft(struct hisi_qm *qm, uint32_t function,
static TEE_Result qm_set_xqc_vft(struct hisi_qm *qm, uint32_t function,
uint32_t base, uint32_t num)
{
int32_t ret = 0;
uint32_t ret = 0;
int32_t i = 0;

if (!num) {
EMSG("Invalid sq num");
return -HISI_QM_DRVCRYPT_EINVAL;
return HISI_QM_DRVCRYPT_EINVAL;
}

for (i = QM_SQC_VFT; i <= QM_CQC_VFT; i++) {
Expand All @@ -263,10 +263,10 @@ static int32_t qm_set_xqc_vft(struct hisi_qm *qm, uint32_t function,
return HISI_QM_DRVCRYPT_NO_ERR;
}

static int32_t qm_get_vft(struct hisi_qm *qm, uint32_t *base, uint32_t *num)
static TEE_Result qm_get_vft(struct hisi_qm *qm, uint32_t *base, uint32_t *num)
{
uint64_t sqc_vft = 0;
int32_t ret = 0;
uint32_t ret = 0;

ret = qm_mb(qm, QM_MB_CMD_SQC_VFT, 0, 0, QM_MB_OP_RD);
if (ret)
Expand All @@ -287,24 +287,24 @@ static void qp_memory_uninit(struct hisi_qm *qm, uint32_t id)
free(qp->cqe);
}

static int32_t qp_memory_init(struct hisi_qm *qm, uint32_t id)
static TEE_Result qp_memory_init(struct hisi_qm *qm, uint32_t id)
{
size_t sq_size = qm->sqe_size * HISI_QM_Q_DEPTH;
size_t cq_size = sizeof(struct qm_cqe) * HISI_QM_Q_DEPTH;
struct hisi_qp *qp = &qm->qp_array[id];
int32_t ret = 0;
uint32_t ret = 0;

qp->sqe = memalign(HISI_QM_ALIGN128, sq_size);
if (!qp->sqe) {
EMSG("Fail to malloc sq[%"PRIu32"]", id);
return -HISI_QM_DRVCRYPT_ENOMEM;
return HISI_QM_DRVCRYPT_ENOMEM;
}
qp->sqe_dma = virt_to_phys(qp->sqe);
assert(qp->sqe_dma);
qp->cqe = memalign(HISI_QM_ALIGN32, cq_size);
if (!qp->cqe) {
EMSG("Fail to malloc cq[%"PRIu32"]", id);
ret = -HISI_QM_DRVCRYPT_ENOMEM;
ret = HISI_QM_DRVCRYPT_ENOMEM;
goto free_sqe;
}
qp->cqe_dma = virt_to_phys(qp->cqe);
Expand All @@ -331,12 +331,13 @@ static void qm_memory_uninit(struct hisi_qm *qm)
free(qm->cqc);
}

static int32_t qm_memory_init(struct hisi_qm *qm)
static TEE_Result qm_memory_init(struct hisi_qm *qm)
{
size_t sqc_size = 0;
size_t cqc_size = 0;
size_t qp_size = 0;
int32_t j, ret;
int32_t j = 0;
uint32_t ret = 0;
uint32_t i;

sqc_size = sizeof(struct qm_sqc) * qm->qp_num;
Expand All @@ -346,14 +347,14 @@ static int32_t qm_memory_init(struct hisi_qm *qm)
qm->sqc = memalign(HISI_QM_ALIGN32, sqc_size);
if (!qm->sqc) {
EMSG("Fail to malloc sqc");
return -HISI_QM_DRVCRYPT_ENOMEM;
return HISI_QM_DRVCRYPT_ENOMEM;
}
qm->sqc_dma = virt_to_phys(qm->sqc);
assert(qm->sqc_dma);
qm->cqc = memalign(HISI_QM_ALIGN32, cqc_size);
if (!qm->cqc) {
EMSG("Fail to malloc cqc");
ret = -HISI_QM_DRVCRYPT_ENOMEM;
ret = HISI_QM_DRVCRYPT_ENOMEM;
goto free_sqc;
}
qm->cqc_dma = virt_to_phys(qm->cqc);
Expand All @@ -362,14 +363,14 @@ static int32_t qm_memory_init(struct hisi_qm *qm)
qm->qp_array = (struct hisi_qp *)malloc(qp_size);
if (!qm->qp_array) {
EMSG("Fail to malloc qp_array");
ret = -HISI_QM_DRVCRYPT_ENOMEM;
ret = HISI_QM_DRVCRYPT_ENOMEM;
goto free_cqc;
}

for (i = 0; i < qm->qp_num; i++) {
ret = qp_memory_init(qm, i);
if (ret) {
ret = -HISI_QM_DRVCRYPT_ENOMEM;
ret = HISI_QM_DRVCRYPT_ENOMEM;
goto free_qp_mem;
}
}
Expand All @@ -387,9 +388,9 @@ static int32_t qm_memory_init(struct hisi_qm *qm)
return ret;
}

int32_t hisi_qm_init(struct hisi_qm *qm)
TEE_Result hisi_qm_init(struct hisi_qm *qm)
{
int32_t ret = 0;
uint32_t ret = 0;

if (qm->fun_type == HISI_QM_HW_VF) {
ret = qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
Expand All @@ -401,7 +402,7 @@ int32_t hisi_qm_init(struct hisi_qm *qm)

if (qm->qp_num == 0 || qm->sqe_size == 0) {
EMSG("Invalid qm parameters");
return -HISI_QM_DRVCRYPT_EINVAL;
return HISI_QM_DRVCRYPT_EINVAL;
}

ret = qm_memory_init(qm);
Expand Down Expand Up @@ -434,7 +435,7 @@ void hisi_qm_uninit(struct hisi_qm *qm)
mutex_destroy(&qm->qp_lock);
}

static int32_t qm_hw_mem_reset(struct hisi_qm *qm)
static TEE_Result qm_hw_mem_reset(struct hisi_qm *qm)
{
uint32_t val = 0;

Expand All @@ -445,20 +446,20 @@ static int32_t qm_hw_mem_reset(struct hisi_qm *qm)
POLL_TIMEOUT);
}

static int32_t qm_func_vft_cfg(struct hisi_qm *qm)
static TEE_Result qm_func_vft_cfg(struct hisi_qm *qm)
{
uint32_t q_base = qm->qp_num;
uint32_t act_q_num = 0;
uint32_t i = 0;
uint32_t j = 0;
int32_t ret = 0;
uint32_t ret = 0;

if (qm->vfs_num == 0)
return HISI_QM_DRVCRYPT_NO_ERR;

if (qm->vfs_num > HISI_QM_MAX_VFS_NUM) {
EMSG("Invalid QM vfs_num");
return -HISI_QM_DRVCRYPT_EINVAL;
return HISI_QM_DRVCRYPT_EINVAL;
}

for (i = 1; i <= qm->vfs_num; i++) {
Expand All @@ -475,9 +476,9 @@ static int32_t qm_func_vft_cfg(struct hisi_qm *qm)
return HISI_QM_DRVCRYPT_NO_ERR;
}

int32_t hisi_qm_start(struct hisi_qm *qm)
TEE_Result hisi_qm_start(struct hisi_qm *qm)
{
int32_t ret = 0;
uint32_t ret = 0;

if (qm->fun_type == HISI_QM_HW_PF) {
ret = qm_hw_mem_reset(qm);
Expand Down Expand Up @@ -542,7 +543,7 @@ void hisi_qm_dev_init(struct hisi_qm *qm)
HISI_QM_ABNML_INT_MASK_CFG);
}

static int32_t qm_sqc_cfg(struct hisi_qp *qp)
static TEE_Result qm_sqc_cfg(struct hisi_qp *qp)
{
struct hisi_qm *qm = qp->qm;
struct qm_sqc *sqc = NULL;
Expand All @@ -551,7 +552,7 @@ static int32_t qm_sqc_cfg(struct hisi_qp *qp)

sqc = memalign(HISI_QM_ALIGN32, sizeof(struct qm_sqc));
if (!sqc)
return -HISI_QM_DRVCRYPT_ENOMEM;
return HISI_QM_DRVCRYPT_ENOMEM;

sqc_dma = virt_to_phys(sqc);
assert(sqc_dma);
Expand All @@ -571,7 +572,7 @@ static int32_t qm_sqc_cfg(struct hisi_qp *qp)
return ret;
}

static int32_t qm_cqc_cfg(struct hisi_qp *qp)
static TEE_Result qm_cqc_cfg(struct hisi_qp *qp)
{
struct hisi_qm *qm = qp->qm;
struct qm_cqc *cqc = NULL;
Expand All @@ -580,7 +581,7 @@ static int32_t qm_cqc_cfg(struct hisi_qp *qp)

cqc = memalign(HISI_QM_ALIGN32, sizeof(struct qm_cqc));
if (!cqc)
return -HISI_QM_DRVCRYPT_ENOMEM;
return HISI_QM_DRVCRYPT_ENOMEM;

cqc_dma = virt_to_phys(cqc);
assert(cqc_dma);
Expand Down Expand Up @@ -666,15 +667,15 @@ static void qm_sq_tail_update(struct hisi_qp *qp)
* One task thread will just bind to one hardware queue, and
* hardware does not support msi. So we have no lock here.
*/
int32_t hisi_qp_send(struct hisi_qp *qp, void *msg)
TEE_Result hisi_qp_send(struct hisi_qp *qp, void *msg)
{
struct hisi_qm *qm = NULL;
int32_t ret = 0;
uuint32_t ret = 0;
void *sqe = NULL;

if (!qp) {
EMSG("qp is NULL");
return -HISI_QM_DRVCRYPT_EINVAL;
return HISI_QM_DRVCRYPT_EINVAL;
}

qm = qp->qm;
Expand Down Expand Up @@ -710,11 +711,11 @@ static void qm_cq_head_update(struct hisi_qp *qp)
}

#define HISI_QM_RECV_DONE 1
static int32_t hisi_qp_recv(struct hisi_qp *qp, void *msg)
static TEE_Result hisi_qp_recv(struct hisi_qp *qp, void *msg)
{
struct hisi_qm *qm = qp->qm;
struct qm_cqe *cqe = NULL;
int32_t ret = 0;
uint32_t ret = 0;
void *sqe = NULL;

ret = qm->dev_status_check(qm);
Expand All @@ -723,8 +724,7 @@ static int32_t hisi_qp_recv(struct hisi_qp *qp, void *msg)

cqe = qp->cqe + qp->cq_head;
if (QM_CQE_PHASE(cqe) == qp->cqc_phase) {
// TODO
__asm__ volatile("dmb osh");
dsb_osh();
sqe = (void *)((vaddr_t)qp->sqe + qm->sqe_size * cqe->sq_head);
ret = qp->parse_sqe(sqe, msg);
qm_cq_head_update(qp);
Expand Down Expand Up @@ -755,14 +755,14 @@ static void qm_dfx_dump(struct hisi_qm *qm)
}
}

int32_t hisi_qp_recv_sync(struct hisi_qp *qp, void *msg)
TEE_Result hisi_qp_recv_sync(struct hisi_qp *qp, void *msg)
{
uint32_t cnt = 0;
int32_t ret = 0;
uint32_t ret = 0;

if (!qp) {
EMSG("qp is NULL");
return -HISI_QM_DRVCRYPT_EINVAL;
return HISI_QM_DRVCRYPT_EINVAL;
}

while (true) {
Expand All @@ -771,7 +771,7 @@ int32_t hisi_qp_recv_sync(struct hisi_qp *qp, void *msg)
if (++cnt > HISI_QM_RECV_SYNC_TIMEOUT) {
EMSG("qm recv task timeout");
qm_dfx_dump(qp->qm);
ret = -HISI_QM_DRVCRYPT_ETMOUT;
ret = HISI_QM_DRVCRYPT_ETMOUT;
break;
}
} else if (ret < 0) {
Expand Down
6 changes: 5 additions & 1 deletion core/drivers/crypto/hisilicon/include/hisi_cipher.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,11 @@ enum C_MODE {

static inline uint32_t multiple_round(uint32_t x, uint32_t y)
{
return (x + y - 1) / y;
uint32_t res = 0;

assert(!ADD_OVERFLOW(x, y - 1, &res));

return res;
}

struct sec_cipher_ctx {
Expand Down
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