[review] core: arm: add boot_cached_mem_end

Update.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

core/arch/arm/kernel/entry_a64.S

@@ -200,7 +200,7 @@ FUNC _start , :
 	/* Copy backwards (as memmove) in case we're overlapping */
 	add	x0, x0, x2		/* __init_start + len */
 	add	x1, x1, x2		/* __data_end + len */
-	adr	x3, cached_mem_end
+	adr_l	x3, boot_cached_mem_end
 	str	x0, [x3]
 	adr	x2, __init_start
 copy_init:
@@ -229,7 +229,7 @@ copy_init:
 	/* Copy backwards (as memmove) in case we're overlapping */
 	add	x1, x1, x2
 	add	x2, x0, x2
-	adr	x3, cached_mem_end
+	adr_l	x3, boot_cached_mem_end
 	str	x2, [x3]
 
 copy_init:
@@ -296,7 +296,8 @@ clear_nex_bss:
 	 * entries used by for instance ARM Trusted Firmware.
 	 */
 	adr_l	x0, __text_start
-	ldr	x1, cached_mem_end
+	adr_l	x1, boot_cached_mem_end
+	ldr	x1, [x1]
 	sub	x1, x1, x0
 	bl	dcache_cleaninv_range
 
@@ -356,10 +357,10 @@ clear_nex_bss:
 	ldr	x0, boot_mmu_config + CORE_MMU_CONFIG_MAP_OFFSET
 	cbz	x0, 1f
 	/*
-	 * Update cached_mem_end address with load offset since it was
+	 * Update boot_cached_mem_end address with load offset since it was
 	 * calculated before relocation.
 	 */
-	adr	x5, cached_mem_end
+	adr_l	x5, boot_cached_mem_end
 	ldr	x6, [x5]
 	add	x6, x6, x0
 	str	x6, [x5]
@@ -453,7 +454,8 @@ clear_nex_bss:
 	 * D-cache before exiting to normal world.
 	 */
 	adr_l	x0, __text_start
-	ldr	x1, cached_mem_end
+	adr_l	x1, boot_cached_mem_end
+	ldr	x1, [x1]
 	sub	x1, x1, x0
 	bl	dcache_cleaninv_range
 
@@ -494,13 +496,9 @@ clear_nex_bss:
 END_FUNC _start
 DECLARE_KEEP_INIT _start
 
+#ifndef CFG_WITH_PAGER
 	.section .identity_map.data
 	.balign	8
-LOCAL_DATA cached_mem_end , :
-	.skip	8
-END_DATA cached_mem_end
-
-#ifndef CFG_WITH_PAGER
 LOCAL_DATA boot_embdata_ptr , :
 	.skip	8
 END_DATA boot_embdata_ptr