drivers: caam: add caam_hal_rng_pr_enabled() for 8QX, 8DX platforms

The SECO firmware enables the RNG prediction resistance by default.
There is no need to read the CAAM RNG status registers.

Signed-off-by: Sahil Malhotra <sahil.malhotra@nxp.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Clement Faure <clement.faure@nxp.com>

core/drivers/crypto/caam/hal/common/hal_rng.c

@@ -62,7 +62,10 @@ bool caam_hal_rng_key_loaded(vaddr_t baseaddr)
 	return io_caam_read32(baseaddr + RNG_STA) & RNG_STA_SKVN;
 }
 
-bool caam_hal_rng_pr_enabled(vaddr_t baseaddr)
+/*
+ * This function will be overridden for i.MX8QX and i.MX8DX platforms.
+ */
+bool __weak caam_hal_rng_pr_enabled(vaddr_t baseaddr)
 {
 	uint32_t bitmask = RNG_STA_PR0;
 

core/drivers/crypto/caam/hal/imx_8q/hal_rng.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: BSD-2-Clause
 /*
- * Copyright 2020-2021 NXP
+ * Copyright 2020-2021, 2024 NXP
  */
 #include <caam_hal_rng.h>
 #include <caam_status.h>
@@ -18,3 +18,12 @@ enum caam_status caam_hal_rng_instantiated(vaddr_t baseaddr __unused)
 	else
 		return CAAM_NO_ERROR;
 }
+
+bool caam_hal_rng_pr_enabled(vaddr_t baseaddr __unused)
+{
+	/*
+	 * On platforms i.MX8Q and i.MX8DXL CAAM RNG Prediction
+	 * resistance is enabled by default. So returning true.
+	 */
+	return true;
+}