driver: crypto: hisilicon: update qm init configs

1. add qm_disable_clock_gate for QM_HW_V3
2. set doorbell timeout to QM_DB_TIMEOUT_SET ns

Signed-off-by: Zexi Yu <yuzexi@hisilicon.com>
Acked-by: Jens Wiklander <jens.wiklander@linaro.org>
Acked-by: Etienne Carriere <etienne.carriere@foss.st.com>

core/drivers/crypto/hisilicon/hisi_qm.c

@@ -67,6 +67,10 @@
 #define QM_CACHE_CFG		0x4893
 #define QM_CACHE_WB_START	0x204
 #define QM_CACHE_WB_DONE	0x208
+#define QM_PM_CTRL0		0x100148
+#define QM_IDLE_DISABLE		BIT(9)
+#define QM_DB_TIMEOUT_CFG	0x100074
+#define QM_DB_TIMEOUT_SET	0x1fffff
 /* XQC shift */
 #define QM_SQ_SQE_SIZE_SHIFT	12
 #define QM_SQ_ORDER_SHIFT	4
@@ -617,11 +621,22 @@ enum hisi_drv_status hisi_qm_start(struct hisi_qm *qm)
 	return HISI_QM_DRVCRYPT_NO_ERR;
 }
 
+static void qm_disable_clock_gate(struct hisi_qm *qm)
+
+{
+	if (qm->version == HISI_QM_HW_V2)
+		return;
+
+	io_setbits32(qm->io_base + QM_PM_CTRL0, QM_IDLE_DISABLE);
+}
+
 void hisi_qm_dev_init(struct hisi_qm *qm)
 {
 	if (qm->fun_type == HISI_QM_HW_VF)
 		return;
 
+	qm_disable_clock_gate(qm);
+
 	/* QM user domain */
 	io_write32(qm->io_base + QM_ARUSER_M_CFG_1, QM_AXUSER_CFG);
 	io_write32(qm->io_base + QM_ARUSER_M_CFG_ENABLE, AXUSER_M_CFG_ENABLE);
@@ -639,6 +654,8 @@ void hisi_qm_dev_init(struct hisi_qm *qm)
 	/* Disable QM ras */
 	io_write32(qm->io_base + HISI_QM_ABNML_INT_MASK,
 		   HISI_QM_ABNML_INT_MASK_CFG);
+	/* Set doorbell timeout to QM_DB_TIMEOUT_SET ns */
+	io_write32(qm->io_base + QM_DB_TIMEOUT_CFG, QM_DB_TIMEOUT_SET);
 }
 
 static enum hisi_drv_status qm_sqc_cfg(struct hisi_qp *qp)