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Verilog-Code

This repository is an effort to make an introduction in SystemVerilog.

Start from Verilog folder first:

graph TD;
    Verilog-->SystemVerilog;
    Verilog-->Verilog-A;
    Verilog-A-->Verilog-AMS;
    SystemVerilog-->SystemVerilog-AMS;
    Verilog-AMS-->SystemVerilog-AMS;
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To Do List

  • fix the readme
  • fix the site make it more readable if possible use a Framework
  • add circuits to acompany the verilog snipets
  • continue the tutorial
  • add more resources

Basic differences

Verilog (HDL | digital | Icarus Verilog)

  • modules

    • input/output/inout

    • reg/wire

    • always block

    • assign

  • testbenches(also modules)

    • timescale

    • always block for clk

    • initial block

SystemVerilog (HDL | digital | Modelsim)

  • modules

    • input/output/inout (do not use: inout)

    • reg/wire/logic (use: logic)

    • always/ always_comb/always_ff blocks (do not use: always block)

    • assign

  • testbenches(also modules)

    • timescale (do not use)

    • always block for clk (prefer this)

    • initial block

    • task

Verilog-A (analog | LTSPICE)

  • modules

    • input/output/inout

    • electrical

    • analog / analog function blocks (prefer: analog block)

    • assign

  • testbench is a circuit (must be drawn)

Verilog-AMS (analog + digital | QUCS Studio)

  • modules

    • input/output/inout

    • reg/wire/electrical

    • always/ always_comb/always_ff blocks (do not use: always block)

    • analog / analog function blocks (prefer: analog block)

    • assign

  • include :

    • constants.vams

    • disciplines.vams

  • testbench is a circuit (must be drawn)

Sources that helped me starting learning HDL:

No. Sources Verilog SystemVerilog UVM VHDL SystemC
1 https://fpgatutorial.com/ ✔️ ✔️ ✔️ ✔️
2 https://www.doulos.com/knowhow/ ✔️ ✔️ ✔️ ✔️
3 https://verificationguide.com/ ✔️ ✔️ ✔️
4 https://www.chipverify.com/ ✔️ ✔️ ✔️
5 https://www.systemverilog.in/p/systemverilog-tutorial.html ✔️ ✔️
6 https://www.fpga4student.com/ ✔️ ✔️
7 https://github.com/JeffDeCola/my-verilog-examples ✔️
8 https://systemverilogdesign.com/tag/multiply/ ✔️ ✔️
9 Digital Design , M. Morris Mano and Michael Ciletti , 6th Ed. ✔️ ✔️ ✔️
10 Digital Design , William J. Dally and R. Curtis Harting ✔️
... ... ... ... ... ... ...

Additional information:

  1. Configuration instructions:

    • No configurations necessary.
  2. Installation instructions:

  3. Operating instructions:

    • Add Icarus Verilog to PATH.
    • Always use flag: -g2012
  4. A file manifest (list of files included):

    Verilog

    > intro

    > tutorial

    Verilog-A

    > intro

    > tutorial

    Verilog-AMS

    > intro

    > tutorial

    SystemVerilog

    > course-material

    > tutorial

    > projects

  5. Copyright and licensing information:

    • See sources table.
  6. Contact information:

    • git
    • mail
  7. Known bugs:

    • No bugs yet.
  8. Troubleshooting:

    • See each folder.
  9. ToDo list:

  • Fix folders
  • Add simple examples
  • add basic modules
  • add comments
  • add testbenches with multiple tests and add explaination
  • complete the readme files
  • find projects and create folders with readme files explaining the project