drivers: clk: sam: extend the time for waiting PLL ready

The start-up time (simulation data) of sama7g5 PLL is 50us in condition
reaching 95% of target frequency. The PLL lock status bit is not set a few
times with current timeout setting. Extend the time to make sure the check
is successful for any cases.

Signed-off-by: Tony Han <tony.han@microchip.com>

core/drivers/clk/sam/clk-sam9x60-pll.c

@@ -62,7 +62,7 @@ struct sam9x60_div {
 		uint32_t __timeout = 0; \
 		uint32_t _c = 0; \
 		\
-		while (__timeout++ < 500) { \
+		while (__timeout++ < 1000) { \
 			_c = io_read32((_base) + AT91_PMC_PLL_ISR0) & \
 				BIT(_id); \
 			if (_c) \