plat-sam: implement PL310 SMC protocol

When Linux runs in normal world, it expects the PL310 to be initially
disabled, and then invokes SMCs to enable it.
Let CFG_PL310_SIP_PROTOCOL=y, and the L2 cache will be left untouched
until the OS enables it.

Signed-off-by: Tony Han <tony.han@microchip.com>

core/arch/arm/plat-sam/conf.mk

@@ -25,6 +25,7 @@ include core/arch/arm/cpu/cortex-a5.mk
 $(call force,CFG_SAMA5D2,y)
 $(call force,CFG_ATMEL_SAIC,y)
 $(call force,CFG_PL310,y)
+$(call force,CFG_PL310_SIP_PROTOCOL,y)
 endif
 
 $(call force,CFG_TEE_CORE_NB_CORE,1)

core/arch/arm/plat-sam/nsec-service/sm_platform_handler.c

@@ -10,13 +10,34 @@
 #include <kernel/tee_misc.h>
 #include <mm/core_memprot.h>
 #include <sam_sfr.h>
+#include <sam_pl310.h>
 #include <sm/optee_smc.h>
 #include <sm/sm.h>
 #include <smc_ids.h>
 
 static enum sm_handler_ret sam_sip_handler(struct thread_smc_args *args)
 {
+	/*
+	* As all sama5 SoCs are single-core ones, check the code compiled for a
+	* single core. No serializations done to protect against concurrency.
+	*/
+	static_assert(CFG_TEE_CORE_NB_CORE == 1);
+
 	switch (OPTEE_SMC_FUNC_NUM(args->a0)) {
+#ifdef CFG_PL310_SIP_PROTOCOL
+	case SAM_SMC_SIP_PL310_ENABLE:
+		args->a0 = pl310_enable();
+		break;
+	case SAM_SMC_SIP_PL310_DISABLE:
+		args->a0 = pl310_disable();
+		break;
+	case SAM_SMC_SIP_PL310_EN_WRITEBACK:
+		args->a0 = pl310_enable_writeback();
+		break;
+	case SAM_SMC_SIP_PL310_DIS_WRITEBACK:
+		args->a0 = pl310_disable_writeback();
+		break;
+#endif
 	case SAMA5_SMC_SIP_SFR_SET_USB_SUSPEND:
 		atmel_sfr_set_usb_suspend(args->a1);
 		args->a0 = SAMA5_SMC_SIP_RETURN_SUCCESS;

core/arch/arm/plat-sam/nsec-service/smc_ids.h

@@ -8,6 +8,11 @@
 #include <optee_msg.h>
 #include <sm/optee_smc.h>
 
+#define SAM_SMC_SIP_PL310_ENABLE	1
+#define SAM_SMC_SIP_PL310_DISABLE	2
+#define SAM_SMC_SIP_PL310_EN_WRITEBACK	3
+#define SAM_SMC_SIP_PL310_DIS_WRITEBACK	4
+
 #define SAMA5_SMC_SIP_SCMI_CALL_ID	0x200
 
 #define SAMA5_SMC_SIP_SFR_SET_USB_SUSPEND	0x300

core/arch/arm/plat-sam/sam_pl310.c

@@ -33,8 +33,14 @@
 #include <mm/core_mmu.h>
 #include <sama5d2.h>
 #include <sam_sfr.h>
+#include <sam_pl310.h>
+#include <sm/optee_smc.h>
 #include <types_ext.h>
 
+/* L2 Cache Controller (L2CC) */
+#define L2CC_DCR_DWB	BIT(1) /* Disable Write-back, Force Write-through */
+#define L2CC_DCR_DCL	BIT(0) /* Disable Cache Linefill */
+
 register_phys_mem_pgdir(MEM_AREA_IO_SEC, PL310_BASE, CORE_MMU_PGDIR_SIZE);
 
 vaddr_t pl310_base(void)
@@ -66,3 +72,41 @@ void arm_cl2_enable(vaddr_t pl310_base)
 	/* Enable PL310 ctrl -> only set lsb bit */
 	io_write32(pl310_base + PL310_CTRL, 1);
 }
+
+#ifdef CFG_PL310_SIP_PROTOCOL
+TEE_Result pl310_enable(void)
+{
+	vaddr_t base = pl310_base();
+
+	arm_cl2_config(base);
+	arm_cl2_enable(base);
+
+	return OPTEE_SMC_RETURN_OK;
+}
+
+TEE_Result pl310_disable(void)
+{
+	EMSG("not implemented");
+
+	return OPTEE_SMC_RETURN_ENOTAVAIL;
+}
+
+TEE_Result pl310_enable_writeback(void)
+{
+	vaddr_t base = pl310_base();
+
+	io_write32(base + PL310_DEBUG_CTRL, 0);
+
+	return OPTEE_SMC_RETURN_OK;
+}
+
+TEE_Result pl310_disable_writeback(void)
+{
+	uint32_t val = L2CC_DCR_DWB | L2CC_DCR_DCL;
+	vaddr_t base = pl310_base();
+
+	io_write32(base + PL310_DEBUG_CTRL, val);
+
+	return OPTEE_SMC_RETURN_OK;
+}
+#endif

core/arch/arm/plat-sam/sam_pl310.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2024, Microchip Technology Inc. and its subsidiaries.
+ */
+
+#ifndef __SAM_PL310_H__
+#define __SAM_PL310_H__
+
+TEE_Result pl310_enable(void);
+TEE_Result pl310_disable(void);
+TEE_Result pl310_enable_writeback(void);
+TEE_Result pl310_disable_writeback(void);
+
+#endif /* __SAM_PL310_H__ */