Fixed typos in loadpair instructions

XUANTIE-RV · Aug 31, 2024 · 9edfb1b · 9edfb1b
1 parent c79b6e5
commit 9edfb1b
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Showing 3 changed files with 3 additions and 3 deletions.
diff --git a/xtheadmempair/ldd.adoc b/xtheadmempair/ldd.adoc
@@ -35,7 +35,7 @@ case the whole instruction will be re-executed.
 Operation::
 [source,sail]
 --
-if (rs1 != rd1 && rs != rd2 && rd1 != rd2) {
+if (rs1 != rd1 && rs1 != rd2 && rd1 != rd2) {
     addr := rs1 + (zero_extend(imm2) << 4)
     tmp1 := mem[addr+7:addr]
     tmp2 := mem[addr+15:addr+8]

diff --git a/xtheadmempair/lwd.adoc b/xtheadmempair/lwd.adoc
@@ -35,7 +35,7 @@ case the whole instruction will be re-executed.
 Operation::
 [source,sail]
 --
-if (rs1 != rd1 && rs != rd2 && rd1 != rd2) {
+if (rs1 != rd1 && rs1 != rd2 && rd1 != rd2) {
     addr := rs1 + (zero_extend(imm2) << 3)
     tmp1 := sign_extend(mem[addr+3:addr])
     tmp2 := sign_extend(mem[addr+7:addr+4])

diff --git a/xtheadmempair/lwud.adoc b/xtheadmempair/lwud.adoc
@@ -35,7 +35,7 @@ case the whole instruction will be re-executed.
 Operation::
 [source,sail]
 --
-if (rs1 != rd1 && rs != rd2 && rd1 != rd2) {
+if (rs1 != rd1 && rs1 != rd2 && rd1 != rd2) {
     addr := rs1 + (zero_extend(imm2) << 3)
     tmp1 := zero_extend(mem[addr+3:addr])
     tmp2 := zero_extend(mem[addr+7:addr+4])