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While using EDIFNetlist methods to read the logical nets from a DCP, I encountered some differences in the total number of nets that I read directly using Tcl in Vivado, and am trying to find out why.
Design: the built-in CPU (HDL) example in Vivado.
I implemented it in Vivado and used one of the resulting "top_opt.dcp" DCPs for this experiment.
Steps:
In Vivado,
get_nets -hier
Using RapidWright,
Map<String,String> parent_net_map = edif_netlist.getParentNetMapNames();
for (String net : parent_net_map.keySet()) {
...
The logical nets returned by Tcl (96874 nets) include four nets that are missing from the EDIFNetlist output (96870 nets), namely:
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Hi,
While using EDIFNetlist methods to read the logical nets from a DCP, I encountered some differences in the total number of nets that I read directly using Tcl in Vivado, and am trying to find out why.
Design: the built-in CPU (HDL) example in Vivado.
I implemented it in Vivado and used one of the resulting "top_opt.dcp" DCPs for this experiment.
Steps:
The logical nets returned by Tcl (96874 nets) include four nets that are missing from the EDIFNetlist output (96870 nets), namely:
Examining the EDIF file, the portion containing the "missing nets" looks like:
whereas a logical net that isn't missing is defined like this:
Do the EDIF differences explain why EDIFNetlist doesn't seem to recognize some nets as such?
What is a good way to reconcile such differences?
Attaching the DCP and EDIF files in case they are helpful.
Thanks,
top_opt.zip
Harnhua
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