Discussions

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  ./gradlew compileJava about environment configuration

  ccZhao-stu started Jul 17, 2024 in General

  

  

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  install and setup issue

  ccZhao-stu asked Jul 16, 2024 in Q&A · Closed · Answered

  

  

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  How to get flat netlist from design checkpoint generated from vivado synthesis？

  wengwz asked Jun 13, 2024 in Q&A · Answered

  

  

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  Source and Sink Pins for Internally Routed (Intra-Site) Nets

  sma-asghar asked Mar 15, 2024 in Q&A · Unanswered

  

  

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  Merging 3 independent DCPs from separate SLRs

  adambagley asked Jan 20, 2024 in Q&A · Answered

  

  

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  How to check all properties and corresponding values of UNISIM cell?

  dg-deus asked Nov 9, 2023 in Q&A · Answered

  

  

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  Using Input Multiplexer (IMUX) Registers (IMRs) on Versal Premium Devices

  oshears asked Oct 10, 2023 in Q&A · Closed · Answered

  

  

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  Runtime-First FPGA Interchange Routing Contest @ FPGA’24

  clavin-xlnx announced Sep 26, 2023 in Announcements

  

  

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  getConnectionPIPs not working for long wires

  sma-asghar asked Aug 31, 2023 in Q&A · Answered

  

  

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  Extract cell connections

  Licheng-Guo asked Aug 15, 2023 in Q&A · Unanswered

  

  

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  How to check whether an EDIFCell is a sequential primitive?

  Licheng-Guo asked Aug 14, 2023 in Q&A · Closed · Answered

  

  

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  Logic Synthesis

  cyberpunksubru asked May 17, 2023 in Q&A · Unanswered

  

  

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  Help understanding routing methods

  codefreak472 asked Apr 6, 2023 in Q&A · Answered

  

  

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  LUT cells get ignored/deleted by Vivado

  codefreak472 asked Mar 27, 2023 in Q&A · Answered

  

  

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  How do I use the BlockPlacer2 to place a design

  burntfalafel asked Mar 18, 2023 in Q&A · Answered

  

  

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  [Feature Request] Accessing Versal BEL Attributes in RapidWright

  nqdtan started Jan 8, 2023 in General · Closed

  

  

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  [Feature Request] Preserve hwdef in DCP file

  nqdtan started Jan 8, 2023 in General · Closed

  

  

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  Seg Fault when running RapidWright in WSL

  ghostlyinfluence asked Oct 3, 2022 in Q&A · Answered

  

  

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  RWRoute and routethru-s

  eddieh-xlnx started Sep 16, 2022 in General

  

  

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  Installation error

  SimonWetzel started Jun 17, 2022 in General · Closed

  

  

  

  

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  How can i store all the LUT and leaf cells used to implement a design in to a text file ?

  SSandeep19 asked Jun 8, 2022 in Q&A · Unanswered

  

  

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  add global nets routing to module checkpoints

  GBrics asked May 18, 2022 in Q&A · Answered

  

  

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  What's the design checkpoint in the example bitstream manipulation code?

  yu-zou asked Jun 6, 2022 in Q&A · Answered

  

  

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  Where is "com.xilinx.rapidwright.bitstream" ?

  tysung asked Dec 17, 2021 in Q&A · Answered

  

  

  

  

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  Issue with Manual Install

  ghostlyinfluence asked May 15, 2022 in Q&A · Unanswered

  

  

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