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This will take some thought and time, I will try to provide an update later in the week on how we might be able to proceed here. |
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In Versal devices, I find that there are some specific BELs whose attributes appear to be read-only to users in Vivado, and could only be set internally by the tool through some optimization phases. Examples are those of IMUX registers, GCLK_DELAY cells, etc. They help the design achieve better timing as far as I understood. The BEL attribute values are stored in a
*.belattrdb
file in a DCP file. If this file is removed from the DCP, Vivado reports a worsen timing slack. Attached is an example of the same design with two different DCPs (one with and the other withoutbelattrdb
), and their respective timing reports. We could observe that the one withbelattrdb
gets better timing result.While RapidWright does preserve the Versal BEL attribute file in DCP, I'd imagine that one may attempt to relocate their design netlist to a different region, thus render the original BEL attributes invalid. Another case is combining multiple DCPs with different
belattrdb
files. There currently seems to be no possible way to modify or update the BEL attributes in accordance with the relocated design netlist. While this issue does not impact the functionality, I'm quite concerned with the negative impact on the performance (achieving lower Fmax) of the relocated design.I think it would be helpful if there is some API in RapidWright that would allow us to parse and modify
belattrdb
.belattrdb_issue
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