How do I use the BlockPlacer2 to place a design #629
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Hi! I have a verilog file which I want to place using RapidWright's framework (maybe if possible routing too). My current flow is
This flow errors out for me at step 2 saying:
Does anyone have a better flow in mind or can suggest corrections to the flow I am using? I have attached the code I am using below for reference. Thanks :)
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Replies: 1 comment
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Hi @burntfalafel, thanks for the question! It turns out that RapidWright currently doesn't have a built-in, fully automatic general placement tool. The One other option is DREAMPlaceFPGA which just added some preliminary support for UltraScale+ designs similar to the GNL design you cited. The process to use it is a bit more involved (need to convert the DCP to bookshelf format, use DREAMPlaceFPGA to place, export as an FPGA Interchange Format result, import back to RapidWright to create a DCP). Directions on how to use it with RapidWright and the FPGA Interchange Format are here: https://github.com/rachelselinar/DREAMPlaceFPGA/tree/main/IFsupport In theory, you could also route the design in RapidWright with our router, RWRoute. There was a recent issue that appears to have been fixed, so its possibly resolved now, I just haven't had a chance to test. |
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Hi @burntfalafel, thanks for the question! It turns out that RapidWright currently doesn't have a built-in, fully automatic general placement tool. The
BlockPlacer2
which you have mentioned is for placing a design composed of pre-implemented modules, which is more of a special case as it is a RapidWright-specific design construct.One other option is DREAMPlaceFPGA which just added some preliminary support for UltraScale+ designs similar to the GNL design you cited. The process to use it is a bit more involved (need to convert the DCP to bookshelf format, use DREAMPlaceFPGA to place, export as an FPGA Interchange Format result, import back to RapidWright to create a DCP). Directions on ho…