Using Input Multiplexer (IMUX) Registers (IMRs) on Versal Premium Devices #848
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Hi RapidWright Team, I'm currently in the process of using RapidWright to create and implement a custom design for Versal. With the Versal architecture, AMD Xilinx has recently added input multiplexer registers to all of their slices (called IMRs). In the image below I've highlighted where these IMR BELs are in relation to the other elements in a SLICEL site. I'd like to (1) use RapidWright to create registers and place them on these IMR BELs, followed by (2) the creation of the Versal device image in Vivado. While I am able to do the first of these aforementioned steps, when I write a checkpoint using RapidWright and attempt to call ERROR: [DRC PDRC-254] SLICE_IMR_FF_use_restricted: Unsupported use of SLICE_X48Y0 site data IMR bel AX_IMR for cell FF_AX_IMR. The register assignment should be changed to a non-IMR FF bel. I am wondering if anyone on your team has been able to successfully write the device image / bitstream for a Versal device that uses these IMR registers? It seems that Vivado is a bit restrictive in their usage and does not make it clear how to instantiate them otherwise. Is there a way that RapidWright can be used to create a design that supports instantiation on these BELs? |
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It looks like you've had a chance to post in the main AMD support forums: https://support.xilinx.com/s/question/0D54U00007PfnLfSAJ/how-to-force-the-use-of-imux-registers-imr-in-a-versal-design?language=en_US with no official answer regarding these IMR resources. We have not attempted to use these resources as they are not supported. Would you be able to elaborate on why you are interested in using them? Perhaps if we can better understand your motivation, we can help you more appropriately. |
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Vivado 2023.2 is available now (https://www.xilinx.com/support/download.html), try using a LOC constraint in Vivado to place the IMR.